Apparatus having three separated and decentralized processors for concurrently and independently processing packets in a communication network

• US 5,465,331 A
• Filed: 12/23/1992
• Issued: 11/07/1995
• Est. Priority Date: 12/23/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Yih, Jih-Shyr, Yang, Michael S.
• Primary Examiner(s): Lim, Krisna
• Application Number:
  US07/996,384
• Time in Patent Office: 1,049 Days
• Field of Search: 370/60, 370/61, 370/94.1, 395/200, 395/325, 395/800
• US Class Current: 709/244
• CPC Class Codes: H04L 12/46 Interconnection of networks
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: H04L 2212/00 Encapsulation of packets
• CPC Class Codes: H04L 49/1523 Parallel switch fabric planes
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 69/00 Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass networks security protocols H04L9/40; wireless communication networks H04W
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A parallel, scalable internetworking unit (IU) architecture employing at least two network controllers (NCs), a foreground buffer controller with local memory, a background buffer controller with local memory, a node processor (NP) and a buffer memory. Each network attached to the IU has an individual network controller which communicates with the foreground buffer controller. The foreground buffer controller interfaces with NCs and maintains queueing information. The background buffer controller communicates with the foreground buffer controller for maintaining packets of data as linked lists of buffers in the buffer memory. The NP communicates with both the foreground and background buffer controllers to process stored header information. And, a connection matrix is provided to dynamically interconnect multiple IUs for increased parallel processing of packet traffic and processing.

Claims

1. In a system having a plurality of networks communicating with packets, a parallel, scalable inter-networking packet routing apparatus for receiving and storing packets from one of the plurality of networks, processing the packets and forwarding packets to another one of the plurality of networks comprising:

a plurality of first control means each first control means for receiving packets from anyone of the plurality of networks, for maintaining a queuing status of the received packets and transferring packets;

a plurality of packet memory means for storing packets received and transferred by the plurality of first control means;

a plurality of second control means, separate from the plurality of first control means, each second control means coupled to an individual one of said plurality of packet memory means, for receiving the transferred packets from a first control means, and for organizing and maintaining packets in respective packet memory means, the plurality of second control means operate concurrently with and independently from the plurality of first control means;

connection switch means, coupled between the plurality of first control means and the plurality of second control means, for transfering packets between any one of the plurality of first control means and any one of the plurality of second control means; and

a plurality of node processor means coupled to a respective first control means and said connection switch means, each node processor means for

     1) obtaining status of the stored packets from the respective first control means,

     2) accessing packets from a packet memory means by way of the connection switch means and a second control means,

     3) processing packets based on their origin and destination,

     4) storing the processed packets back into the packet memory means by way of the connection switch means and the second control means and

     5) for updating the queueing status of the packets by way of the respective first control means, the plurality of node processors operate concurrently with and independently from the first and second control means.

2. The inter-networking packet routing apparatus of claim 1 further providing each of said plurality of networks having a network controller means, each network controller means coupled to one of said plurality of first control means, each of said network controller means for controlling the transmission of packets from its respective network to said first control means and the reception of packets from said first control means to its respective network.

3. The inter-networking packet routing apparatus of claim 1 further providing a plurality of queue memories, each coupled to one of said plurality of first cotrol means and containing a queuing status in the form of queue table entries (QTEs) indicating which packets are ready to be processed by a respective node processor means and which packets are ready to be transferred from a respective packet memory means to one of said plurality of network controller means.

4. The inter-networking packet routing apparatus of claim 3 wherein providing a plurality of packet buffer memories which are used in the maintenance and organization of said packets, each coupled to one of said plurality of second control means and containing packet table entries (PTEs) and buffer table entries (BTEs), each PTE points to a linked list of BTEs which correspond to a plurality of locations in a respective packet memory means containing the packet identified by a QTE.

5. The inter-networking packet routing apparatus of claim 1 wherein said packets comprise a payload and a header, each of said packet memory means comprises first and second memories, wherein said first memory contains packet payloads and said second memory contains packet headers.

6. The inter-networking packet routing apparatus of claim 1, wherein packets are received from one of said plurality of networks and packets are sent to another of said plurality of networks, wherein all of said first control means are coupled via a communication bus.

7. In a system having a plurality of networks communicating with packets, a parallel, scalable inter-networking packet routing apparatus for receiving and storing packets from one of the plurality of networks, processing the packets and forwarding the packets to another of the plurality of networks comprising:

first control means for receiving packets from one of said plurality of networks, for maintaining a queuing status of the received packets and transferring the packets,

packet memory means for storing packets received and transferred by the first control means;

second control means, separate from the first control means and coupled between the first control means and the packet memory means, for receiving the transferred packets from the first control means, and for organizing and maintaining the packets in the packet memory means, the second control means operates concurrently with and independently from the first control means;

node processor means, separate from the first and second control means and coupled to both the first and the second control means for

     1) obtaining status of the stored packets from the first control means,

     2) accessing packets from the packet memory means by request to the second control means,

     3) processing packets based on their origin and destination,

     4) storing the processed packets back into the packet memory means by way of the second control means and

     5) for updating the queueing status of the packets by way of the first control means, the node processor operates concurrently with and independently from the first and second control means,

thereby the first control means, second control means and the node processor means being separated and decentralized of control to provide for parallel operation and scalability.

8. The inter-networking packet routing apparatus of claim 7, wherein said node processor means is directly coupled to said second control means and said first control means.

9. The inter-networking packet routing apparatus of claim 7 further providing each of said plurality of networks having network controller means, each network controller means coupled to said first control means for controlling the transmission of packets from one of said plurality of networks to said first control means and the reception of packets from said first control means to one of said plurality of networks.

10. The inter-networking packet routing apparatus of claim 7 further providing a queue memory coupled to said first control means, said queue memory containing queuing status in the form of queue table entries (QTEs) indicating which packets are ready to be processed by said node processor means and which packets are ready to be transferred from said packet memory means to one of said plurality of network controller means.

11. The inter-networking packet routing apparatus of claim 10 further providing a packet buffer memory coupled to said second control means which is used in the maintenance and organization of said packets, said packet buffer memory containing packet table entries (PTEs) and buffer table entries (BTEs), each PTE points to a linked list of BTEs which correspond to a plurality of locations in the packet memory means containing the packet identified by a QTE.

12. The inter-networking packet routing apparatus of claim 7, wherein said packets comprise a payload and a header, said packet memory means comprises first and second memories, said first memory contains packet payloads and said second memory contains packet headers.