Even order term mixer
First Claim
1. A signal mixer for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixer comprising:
- first mixer means for receiving and mixing first and second ac input signals to provide a first ac mixed signal, wherein said first mixer means is de-biased in a first linear operating region and has a first input impedance associated therewith, and wherein said first and second ac input signals are received at opposing ends of said first input impedance;
second mixer means coupled to said first mixer means for receiving and mixing said first and second ac input signals to provide a second ac mixed signal, wherein said second mixer means is de-biased in a second linear operating region and has a second input impedance associated therewith, and wherein said first and second ac input signals are received at opposing ends of said second input impedance; and
combiner means coupled to said first and second mixer means for receiving and combining said first and second ac mixed signals to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms.
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Accused Products
Abstract
An even order term mixer for mixing two ac input signals includes two bipolar junction transistors (each having a base-emitter junction forward bias threshold voltage VT) with mutually connected collectors and cross-coupled bases and emitters. Each transistor receives a dc emitter bias current IE and both transistors each receive two single-ended ac input signals V1 (=|V1 |.cos[2πf1 t]) and V2 (=|V2 |.cos[2πf2 t]). Each transistor mixes its two ac input signals V1, V2 and produces a collector current representing the result thereof. The two collector currents sum at the interconnected collectors and produce across a resistor RC also connected thereto an ac output voltage V0 having even order terms and virtually no odd order terms of the mixing products (e.g. sum of and difference between the frequencies) of the two ac input signals.
117 Citations
24 Claims
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1. A signal mixer for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixer comprising:
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first mixer means for receiving and mixing first and second ac input signals to provide a first ac mixed signal, wherein said first mixer means is de-biased in a first linear operating region and has a first input impedance associated therewith, and wherein said first and second ac input signals are received at opposing ends of said first input impedance; second mixer means coupled to said first mixer means for receiving and mixing said first and second ac input signals to provide a second ac mixed signal, wherein said second mixer means is de-biased in a second linear operating region and has a second input impedance associated therewith, and wherein said first and second ac input signals are received at opposing ends of said second input impedance; and combiner means coupled to said first and second mixer means for receiving and combining said first and second ac mixed signals to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms. - View Dependent Claims (2, 3, 4)
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5. A signal mixer for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixer comprising:
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a first transistor circuit which includes a first transistor which is dc-biased in a first linear operating region and has associated therewith a first input impedance with first and second opposing ends, a primary input circuit connected to said first end of said first input impedance for receiving a first ac input signal, a secondary input circuit connected to said second end of said first input impedance for receiving a first dc signal and at least part of a second ac input signal, and an output for providing a first ac mixed signal; a second transistor circuit which includes a second transistor which is dc-biased in a second linear operating region and has associated therewith a second input impedance with first and second opposing ends, a primary input circuit connected to said first end of said second input impedance for receiving said second ac input signal, a secondary input circuit connected to said second end of said second input impedance for receiving a second dc signal and at least part of said first ac input signal, and an output for providing a second ac mixed signal, wherein said second transistor circuit output is coupled to said first transistor circuit output; and a resistor coupled to said first and second transistor circuit outputs to receive said first and second ac mixed signals and to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms. - View Dependent Claims (6, 7)
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8. A signal mixer for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixer comprising:
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a first transistor which includes a primary terminal for receiving a first dc signal, a secondary terminal for receiving a first ac input signal, and a tertiary terminal for providing a first ac mixed signal; a second transistor which includes a primary terminal for receiving a second dc signal, a secondary terminal for receiving a second ac input signal, and a tertiary terminal for providing a second ac mixed signal, wherein said tertiary terminal of said second transistor is coupled to said tertiary terminal of said first transistor; a third transistor which includes a primary terminal coupled to said secondary terminal of said second transistor, a secondary terminal coupled to said primary terminal of said first transistor, and a tertiary terminal; a fourth transistor which includes a primary terminal coupled to said secondary terminal of said first transistor, a secondary terminal coupled to said primary terminal of said second transistor, and a tertiary terminal; and a resistor coupled to said tertiary terminals of said first and second transistors to receive said first and second ac mixed signals and to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms. - View Dependent Claims (9)
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10. A signal mixing method for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixing method comprising the steps of:
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inputting first and second ac input signals to opposing ends of an input impedance of a first signal mixer which is dc-biased in a first linear operating region; mixing said first and second ac input signals in said first signal mixer to provide a first ac mixed signal; inputting said first and second ac input signals to opposing ends of an input impedance of a second signal mixer which is dc-biased in a second linear operating region; mixing said first and second ac input signals in said second signal mixer to provide a second ac mixed signal; and combining said first and second ac mixed signals to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms. - View Dependent Claims (11, 12, 13)
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14. A signal mixing method for mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixing method comprising the steps of:
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inputting a first ac input signal to a primary input circuit of a first transistor circuit which includes a first transistor which is dc-biased in a first linear operating region and has associated therewith a first input impedance with first and second opposing ends, wherein said first transistor primary input circuit is connected to said first end of said first input impedance; inputting a first dc signal and at least part of a second ac input signal to a secondary input circuit of said first transistor circuit, wherein said first transistor secondary input circuit is connected to said second end of said first input impedance; outputting a first ac mixed signal from an output of said first transistor circuit; inputting said second ac input signal to a primary input circuit of a second transistor circuit which includes a second transistor which is dc-biased in a second linear operating region and has associated therewith a second input impedance with first and second opposing ends, wherein said second transistor primary input circuit is connected to said first end of said second input impedance; inputting a second dc signal and at least part of said first ac input signal to a secondary input circuit of said second transistor circuit, wherein said second transistor secondary input circuit is connected to said second end of said second input impedance; outputting a second ac mixed signal from an output of said second transistor circuit; inputting said first and second ac mixed signals to a resistor; and outputting from said resistor an ac output signal which includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms. - View Dependent Claims (15, 16)
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17. A signal mixing method for mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixer comprising:
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inputting a first dc signal to a node connecting a primary terminal of a first transistor and a secondary terminal of a third transistor; inputting a first ac input signal to a secondary terminal of said first transistor and to a primary terminal of a fourth transistor; outputting a first ac mixed signal from a tertiary terminal of said first transistor; inputting a second dc signal to a node connecting a primary terminal of a second transistor and secondary terminal of said fourth transistor; inputting a second ac input signal to a secondary terminal of said second transistor and to a primary terminal of said third transistor; outputting a second ac mixed signal from a tertiary terminal of said second transistor; inputting said first and second ac mixed signals to a resistor; and outputting from said resistor an ac output signal which includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms. - View Dependent Claims (18)
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19. A signal mixer for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixer comprising:
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first mixer means for receiving and mixing first and second ac input signals to provide a first ac mixed signal, wherein said first mixer means is dc-biased in a first linear operating region and includes; a first transistor with a primary terminal, a secondary terminal for receiving said second ac input signal and a tertiary terminal for providing said first ac mixed signal, and a second transistor with a primary terminal for receiving said first ac input signal, a secondary terminal coupled to said first transistor primary terminal and a tertiary terminal; second mixer means coupled to said first mixer means for receiving and mixing said first and second ac input signals to provide a second ac mixed signal, wherein said second mixer means is dc-biased in a second linear operating region; and combiner means coupled to said first and second mixer means for receiving and combining said first and second ac mixed signals to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms. - View Dependent Claims (20)
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21. A signal mixer for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixer comprising:
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a first transistor circuit which is dc-biased in a first linear operating region and includes a primary input circuit for receiving a first ac input signal, a secondary input circuit for receiving a first dc signal and at least part of a second ac input signal, and an output for providing a first ac mixed signal; a second transistor circuit which is dc-biased in a second linear operating region and includes a primary input circuit for receiving said second ac input signal, a secondary input circuit for receiving a second dc signal and at least part of said first ac input signal, and an output for providing a second ac mixed signal, wherein said second transistor circuit output is coupled to said first transistor circuit output; and a resistor coupled to said first and second transistor circuit outputs to receive said first and second ac mixed signals and to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms; wherein said first and second transistor circuits comprise first and second bipolar junction transistors, respectively, with each having a base-emitter junction forward bias threshold voltage associated therewith, and further wherein said ac output signal is provided approximately in accordance with;
space="preserve" listing-type="equation">V.sub.0 ≈
-2IR.cosh[(V.sub.1 -V.sub.2)/V.sub.T ]where; V0 =voltage value of said ac output signal I=current value of each of said first and second dc signals R=resistance value of said resistor V1 =voltage value of said first ac input signal V2 =voltage value of said second ac input signal VT =value of said base-emitter junction forward bias threshold voltage cosh[(V1 -V2)/VT ]=hyperbolic cosine of (V1 -V2)/VT.
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22. A signal mixing method for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixing method comprising the steps of:
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inputting first and second ac input signals to a first signal mixer which is dc-biased in a first linear operating region; mixing said first and second ac input signals in said first signal mixer to provide a first ac mixed signal by; inputting said second ac input signal to a secondary terminal of a first transistor, inputting said first ac input signal to a primary terminal of a second transistor, coupling a first intermediate signal from a secondary terminal of said second transistor to a primary terminal of said first transistor, and outputting said first ac mixed signal from a tertiary terminal of said first transistor; inputting said first and second ac input signals to a second signal mixer which is dc-biased in a second linear operating region; mixing said first and second ac input signals in said second signal mixer to provide a second ac mixed signal; and combining said first and second ac mixed signals to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms.
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23. A signal mixing method for mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixing method comprising the steps of:
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inputting a first ac input signal to a primary input circuit of a first transistor circuit which is dc-biased in a first linear operating region; inputting a first dc signal and at least part of a second ac input signal to a secondary input circuit of said first transistor circuit; outputting a first ac mixed signal from an output of said first transistor circuit; inputting said second ac input signal to a primary input circuit of a second transistor circuit which is dc-biased in a second linear operating region; inputting a second dc signal and at least part of said first ac input signal to a secondary input circuit of said second transistor circuit; outputting a second ac mixed signal from an output of said second transistor circuit; inputting said first and second ac mixed signals to a resistor; and outputting from said resistor an ac output signal which includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms; wherein said first and second transistor circuits comprise first and second bipolar junction transistors, respectively, with each having a base-emitter junction forward bias threshold voltage associated therewith, and further wherein said step of outputting an ac output signal comprises outputting said ac output signal approximately in accordance with;
space="preserve" listing-type="equation">V.sub.0 ≈
-2IR.cosh[(V.sub.1 -V.sub.2)/V.sub.T ]where; V0 =voltage value of said ac output signal I=current value of each of said first and second dc signals R=resistance value of said resistor V1 =voltage value of said first ac input signal V2 =voltage value of said second ac input signal VT =value of said base-emitter junction forward bias threshold voltage cosh[(V1 -V2)/VT ]=hyperbolic cosine of (V1 -V2)/VT.
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24. A signal mixing method for receiving and mixing first and second ac input signals, and for providing an ac output signal with even order terms and substantially suppressed odd order terms of the mixing products of said first and second input signals, said signal mixing method comprising the steps of:
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inputting first and second ac input signals to a first signal mixer which is dc-biased in a first linear operating region; mixing said first and second ac input signals in said first signal mixer to provide a first ac mixed signal by; inputting said second ac input signal to a secondary terminal of a first transistor, inputting said first ac input signal to a primary terminal of a second transistor, coupling a first intermediate signal from a secondary terminal of said second transistor to a primary terminal of said first transistor, and outputting said first ac mixed signal from a tertiary terminal of said first transistor; inputting said first and second ac input signals to a second signal mixer which is dc-biased in a second linear operating region; mixing said first and second ac input signals in said second signal mixer to provide a second ac mixed signal by; inputting said first ac input signal to a secondary terminal of a third transistor, inputting said second ac input signal to a primary terminal of a fourth transistor, coupling a second intermediate signal from a secondary terminal of said fourth transistor to a primary terminal of said third transistor, and outputting said second ac mixed signal from a tertiary terminal of said third transistor; combining said first and second ac mixed signals to provide an ac output signal, wherein said ac output signal includes a first plurality of even order terms and a second plurality of odd order terms of mixing products of said first and second ac input signals, and further wherein each of said first plurality of even order terms is greater in magnitude than adjacent ones of said second plurality of odd order terms.
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Specification