Method of making a high-density DRAM structure on SOI

• US 5,466,625 A
• Filed: 11/22/1994
• Issued: 11/14/1995
• Est. Priority Date: 06/17/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis L. C., Ogura, Seiki, Hsieh, Chang-Ming
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/346,207
• Time in Patent Office: 357 Days
• Field of Search: 437/47, 437/48, 437/52, 437/60, 437/203, 437/228, 437/235, 437/919, 437/21, 257/301, 257/302
• US Class Current: 438/155
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.

Claims

1. A method of forming a pair of integrated circuit, shared gate, cells for dynamic random access memories, comprising in combination:

patterning a silicon source layer on a silicon-on oxide wafer comprised of an oxide layer on the upper surface of an underlying support wafer;

etching a pair of capacitor trenches that extend through said patterned silicon source layer and said oxide layer and into said underlying support wafer;

conformally depositing a first capacitor plate layer on the wall of each of said pair of said capacitor trenches, said first capacitor plate layer extending to and connected with said silicon source layer;

forming a capacitor dielectric layer on said polysilicon capacitor plate layer;

forming an silicon channel layer conformally over said capacitor dielectric layer and overlying a region of said silicon source layer, said silicon channel layer forming a second capacitor plate and a channel layer;

forming a polysilicon drain layer overlying said silicon channel layer in said region where said silicon channel layer overlays said silicon source layer;

etching a vertical opening extending through silicon source layer, said silicon channel layer, and said polysilicon drain layer forming a pair of facing vertical wall surfaces in the region where the layers overlay one another with an edge in each layer respectively aligned vertically along said pair of facing vertical wall surfaces, said silicon channel layer extending from one of said facing wall surfaces forming the channel layer and the second capacitor plate layer for one cell of said pair of integrated circuit cells and said silicon channel layer extending from the other of said facing wall surfaces forming the channel layer and the second capacitor plate layer for the other cell of said pair of integrated circuit cells;

forming a gate dielectric covering said pair of facing vertical wall surfaces; and

forming a vertical gate in said opening in contact with said gate dielectric.

2. A method of forming a pair of integrated circuit, shared gate, cells for dynamic random access memories as in claim 1, including the further steps of:

forming a substrate contact region in said silicon substrate layer common to said pair of integrated circuit cells; and

forming a bit-line contact region in said polysilicon drain layer extending from said one of said facing wall surfaces.

3. A method of forming an integrated circuit cell for dynamic random access memories, comprising the steps of:

patterning a silicon source layer on a silicon-on-oxide wafer comprised of an oxide layer on the upper surface of an underlying support wafer;

etching a capacitor trench that extends through said patterned silicon source layer and said oxide layer and into said underlying support wafer;

conformally depositing a first capacitor plate layer on the wall of said capacitor trench, said first capacitor plate layer extending to and connected with said silicon source layer;

forming a capacitor dielectric layer on said first capacitor plate layer;

conformally forming an silicon channel layer over said capacitor dielectric layer and overlying a region of said silicon source layer, said silicon channel layer forming a second capacitor plate and a channel layer;

depositing a polysilicon drain layer overlying said silicon channel layer in said region where said silicon channel layer overlays said silicon source layer;

etching a vertical opening extending through silicon source layer, said silicon channel layer, and said polysilicon drain layer, said vertical opening forming a wall surface in the region where the layers overlay one another with an edge in each layer respectively aligned vertically along said wall surface;

forming a gate dielectric covering said wall surface; and

forming a vertical gate in said opening in contact with said gate dielectric.