Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating

• US 5,466,635 A
• Filed: 06/02/1994
• Issued: 11/14/1995
• Est. Priority Date: 06/02/1994
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Lynch, Brian, O'Brien, Patrick
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US08/252,691
• Time in Patent Office: 530 Days
• Field of Search: 437/183, 228/180.22, 257/737, 257/738, 257/779, 257/781
• US Class Current: 438/614
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/136 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13609 Indium [In] as principal constituent
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H05K 2201/0367 : Metallic bump or raised conductor not used as solder bump
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

An interconnect bump is formed on a substrate structure of a flip-chip microelectronic integrated circuit by sputtering a metal base layer on the substrate, and then forming a copper standoff on the base layer. A solder cap is formed on the standoff having a peripheral portion that extends laterally external of the standoff. The peripheral portion of the cap is used as a self-aligned mask for a photolithographic step that results in removing the metal base layer except under the standoff and the cap. The cap has a lower melting point than the standoff. Heat is applied that is sufficient to cause the cap to melt over and coat the standoff and insufficient to cause the standoff to melt. The peripheral portions of the cap and the base layer that extend laterally external of the standoff cause the melted solder to form into a generally hourglass shape over the standoff due to surface tension.

Claims

1. A method of fabricating an interconnect bump on a substrate structure, comprising the steps of:

(a) forming a standoff on the substrate structure;

forming a cap on the standoff having a peripheral portion that extends laterally external of the standoff, the cap having a lower melting point than the standoff;

(c) applying heat that is sufficient to cause the cad to melt over and coat the standoff and insufficient to cause the standoff to melt; and

(d) prior to step (c), forming a base under the standoff having a peripheral portion that extends laterally external of the standoff, the base being wetted by the cap in step (c);

in which step (d) comprises the substeps of;

(e) forming a base layer on the substrate structure;

(f) forming a photoresist section on a portion of said base layer corresponding to said peripheral portion of the base using said peripheral portion of the cap as a self-aligned mask;

(g) removing said base layer except under said photoresist section to form the base; and

(h) removing said photoresist section.

2. A method as in claim 1, in which steps (a) and (b) comprise forming the standoff and the cap respectively of materials such that the standoff is wetted by the cap in step (c).

3. A method as in claim 1, in which step (b) comprises forming said peripheral portion such that the cap melts over the standoff into a generally hourglass shape in step (c).

4. A method as in claim 1, in which:

step (f) comprises the substeps, performed prior to step (a), of;

(i) forming a photoresist layer on said base layer; and

(j) forming a hole through said photoresist layer;

step (a) comprises forming the standoff in said hole;

step (b) comprises forming the cap on the standoff such that said peripheral portion of the cap extends over said photoresist layer;

step (f) comprises the substeps, performed between steps (b) and (g), of;

(m) exposing said photoresist layer using said peripheral portion of the cap as a self-aligned mask; and

(n) developing said photoresist layer to form said photoresist section; and

step (g) comprises etching away said base layer using an etchant that does not etch said photoresist section to form the base.

5. A method as in claim 4, in which:

step (a) comprises forming the standoff to a thickness that is smaller than a thickness of said photoresist layer such that a recess is formed in said hole above the standoff; and

step (b) comprises forming the cap to a thickness that is larger than a depth of said recess such that the cap extends above said hole.

6. A method of fabricating an interconnect bump on a substrate structure, comprising the steps of:

(a) forming a standoff on the substrate structure;

(b) forming a cap on the standoff having a peripheral portion that extends laterally external of the standoff, the cap having a lower melting point than the standoff; and

(c) applying heat that is sufficient to cause the cap to melt over and coat the standoff and insufficient to cause the standoff to melt; and

(d) prior to step (c), forming a base under the standoff having a peripheral portion that extends laterally external of the standoff, the base being wetted by the cap in step (c);

in which;

step (d) comprises the substeps of;

(e) forming a base layer on the substrate structure;

(f) forming a photoresist section on a portion of said base layer corresponding to said peripheral portion of the base using said peripheral portion of the cap as a self-aligned mask;

(g) removing said base layer except under said photoresist section to form the base; and

(h) removing said photoresist section; and

steps (a) and (b) comprise forming the standoff and the cap of electrically conductive metals respectively that are selected such that the cap wets the standoff in step (c); and

step (a) comprises forming the standoff of a material selected from the group consisting of copper and gold.

7. A method of fabricating an interconnect bump on a substrate structure, comprising the steps of:

(a) forming a standoff on the substrate structure;

(b) forming a cap on the standoff having a peripheral portion that extends laterally external of the standoff, the cap having a lower melting point than the standoff; and

(c) applying heat that is sufficient to cause the cap to melt over and coat the standoff and insufficient to cause the standoff to melt; and

(d) prior to step (c), forming a base under the standoff having a peripheral portion that extends laterally external of the standoff, the base being wetted by the cap in step (c);

in which;

step (d) comprises the substeps of;

(e) forming a base layer on the substrate structure;

(f) forming a photoresist section on a portion of said base layer corresponding to said peripheral portion of the base using said peripheral portion of the cap as a self-aligned mask;

(g) removing said base layer except under said photoresist section to form the base; and

(h) removing said photoresist section; and

steps (a) and (b) comprise forming the standoff and the cap of electrically conductive metals respectively that are selected such that the cap wets the standoff in step (c); and

step (a) comprises forming the cap of a material selected from the group consisting of solder and indium.