Method of making a self-aligned contact in semiconductor device

• US 5,466,637 A
• Filed: 09/08/1993
• Issued: 11/14/1995
• Est. Priority Date: 09/09/1992
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Kim, Jae K.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US08/118,458
• Time in Patent Office: 797 Days
• Field of Search: 437/187, 437/195, 437/44, 437/239, 437/228, 437/52, 437/984, 437/149, 437/150, 437/151
• US Class Current: 438/639
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

A method of making a self-aligned contact in a semiconductor device has some advantages in that the increasing tolerance of contact mask for following the contact hole may lead to reduction of the contact area by the following means: at the side wall of contact hole which connects the first conductive line and the third line up and down, a silicon spacer which insulates from the second conductive line is formed; then, the said spacer in part or whole is thermally oxidized and the upper part of silicon spacer is insulated, thus forming the contact hole thereof.

Claims

1. A method of making a self-aligned contact in a semiconductor device comprising the steps of:

a) forming sequentially a first dielectric layer, a second conductive line, and a second dielectric layer on a semiconductor substrate;

b) forming a contact hole by successively removing the second dielectric layer, the second conductive line and the first dielectric layer from above a region of the semiconductor substrate, thereby exposing the semiconductor substrate, said contact hole thereby having an inner wall surface that includes a sidewall of the second conductive line and a sidewall of the second dielectric layer;

c) forming a first conductive line by depositing impurities into the exposed semiconductor substrate;

d) forming an oxide layer at the side wail of the second conductive line within said contact hole and on the first conductive line;

e) forming a nitride layer on the surface of the oxide layer and the second dielectric layer, the nitride layer thereby having a nitride wall portion within said contact hole, said nitride wall portion On the oxide layer at the sidewall of the second conductive line and on the sidewall of the second dielectric layer;

f) forming a silicon spacer on the nitride wall portion;

g) forming a thermal oxide by thermally oxidizing said silicon spacer to a desired thickness;

h) exposing the first conductive line by removing said nitride layer, oxide layer, and a portion of the thermal oxide layer which are exposed to the inside of the contact hole, and also by removing said nitride layer and the second dielectric layer outside of the contact hole an appropriate thickness, while leaving a substantial thickness of the second dielectric layer and of the thermal oxide formed on the surface of the silicon spacer; and

i) forming a third conductive line contacted with the exposed first conductive line.

2. A method of claim 1, wherein said step for forming the thermal oxide layer is carried out by entirely thermal oxidizing the silicon spacer.

3. A method of claim 1, wherein the thickness of the oxide layer is 50 to 300 Å

, on the first conductive line and the second conductive line.

4. A method of claim 1, wherein the thickness of nitride layer is 100 to 500 Å

.

5. A method of claim 1, wherein said silicon spacer is formed by anisotropic etching, after poly or amorphous silicon layer is formed on the nitride.

6. A method of claim 1, wherein said silicon spacer has a thickness in the range of 500 to 2000 Å

.