Spin motor control system for a hard disk assembly

• US 5,466,997 A
• Filed: 06/15/1993
• Issued: 11/14/1995
• Est. Priority Date: 12/19/1990
• Status: Expired due to Term

• Current Assignee: Mobile Storage Technology Inc
• Original Assignee: Integral Peripherals, Inc.
• Inventors: Utenick, Michael R., Blagaila, John H.
• Primary Examiner(s): Ro, Bentsu
• Application Number:
  US08/075,572
• Time in Patent Office: 882 Days
• Field of Search: 318/560, 318/569, 318/594, 318/600, 318/601, 318/430, 318/431, 318/439, 318/138, 318/254
• US Class Current: 318/400.21
• CPC Class Codes: G11B 19/2009 Turntables, hubs and motors for disk drives; Mounting of motors in the drive means for clamping of disk to turntable G11B17/022 and subgroups
• CPC Class Codes: G11B 19/28 Speed controlling, regulating, or indicating G11B19/24 takes precedence
• CPC Class Codes: H02P 6/21 Open loop start

Abstract

A spin motor control system includes a BEMF commutation circuit, a startup circuit and a monitor circuit, each of which operate utilizing digital techniques. The BEMF commutation circuit includes first and second counters that are programmable to accommodate for changing system parameters. The BEMF commutation circuit does not require the incorporation of an external capacitor, is insensitive to leakage current, and provides stable timing characteristics. The startup circuit also includes a counter and is programmable to accommodate for changing system parameters. The startup circuit does not require an external capacitor and provides stable generation of the startup pulses. The monitor circuit includes first and second counters for blanking the BEMF circuitry after commutation. The monitor circuit further includes circuitry for detecting and correcting the direction of rotation of the spin motor. The monitor circuit provides a microprocessor interface to allow for changing motor parameters and environmental conditions, eliminates the requirement of a capacitor, and provides stable timing characteristics.

Claims

1. A control circuit for a spin motor having a plurality of windings, said control circuit comprising:

a back EMF sensing circuit connectable to at least one winding of said spin motor wherein said back EMF sensing circuit in response to a back EMF induced in said at least one winding generates a back EMF output signal;

a first counter circuit having an input line coupled to said back EMF sensing circuit and an output line coupled to a spin motor sequencer circuit wherein said first counter circuit generates a signal on said output line that is used to commutate a phase of said spin motor;

a second counter circuit having an input line coupled to said back EMF sensing circuit and an output line coupled to said spin motor sequencer circuit wherein said second counter circuit generates a signal on said output line that is used to commutate said phase of said spin motor; and

a microprocessor interface coupled to said first and second counter circuit, for programming a first count value in said first counter circuit, and for programming a second count value in said second counter circuit.

2. The control circuit as recited in claim 1 further comprising a clock circuit for generating a single clock signal to drive both said first and said second counter circuit.

3. The control circuit as recited in claim 2 wherein said first counter circuit further comprises a first count detector coupled to a first counter.

4. The control circuit as recited in claim 3 wherein said second counter circuit further comprises a second count detector coupled to a second counter.

5. The control circuit as recited in claim 4 wherein said first count detector and said second count detector are zero count detectors.

6. The control circuit as recited in claim 3 wherein said first counter circuit further comprises a logic circuit, coupled to said first count detector, for providing a BEMF pulse wherein said BEMF pulse is said signal on said output line of said first counter circuit that is used to commutate a phase of said spin motor.

7. The control circuit as recited in claim 4 wherein said second counter circuit further comprises a second logic circuit, coupled to said second count detector, for providing a BEMF pulse wherein said BEMF pulse is said signal on said output line of said second counter circuit that is used to commutate a phase of said spin motor.

8. A control circuit as recited in claim 1 wherein said back EMF output signal is a tachometer signal.

9. A control circuit for a spin motor having a plurality of windings, said control circuit comprising:

a back EMF sensing circuit connectable to at least one winding of said spin motor wherein said back EMF sensing circuit in response to a back EMF induced in said at least one winding generates a back EMF output signal;

a first counter circuit having an input line coupled to said back EMF sensing circuit and an output line coupled to a spin motor sequencer circuit wherein said first counter circuit generates a signal on said output line that is used to commutate a phase of said spin motor;

a second counter circuit having an input line coupled to said back EMF sensing circuit and an output line coupled to said spin motor sequencer circuit wherein said second counter circuit generates a signal on said output line that is used to commutate said phase of said spin motor;

a microprocessor interface coupled to said first and second counter circuits for programming a first count value in said first counter circuit and for programming a second count value in said second counter circuit;

a start-up circuit including a third counter, and coupled to said spin motor and to said microprocessor interface wherein said start-up circuit starts said spin motor from a stalled condition; and

a monitor circuit including a fourth counter, and coupled to said microprocessor interface and to said spin motor wherein said monitor circuit determines the spin direction of said spin motor.

10. A startup control circuit for a spin motor comprising:

a BEMF generating circuit having an input line coupled to said spin motor so that said input line receives a BEMF signal and an output line wherein said BEMF generating circuit generates a BEMF commutation pulse on said output line in response to said BEMF signal on said input line;

a counter circuit having an input line, a count direction control terminal, and an output line;

wherein said counter circuit changes a count value in response to a signal on said input line;

a startup pulse is generated on said output line upon said count value equaling a predetermined value; and

a signal on said count direction control terminal determines the direction of change of said count value;

a logic circuit having (i) an input line coupled to said output line of said BEMF generating circuit and (ii) an output line connected to said input line of said counter circuit;

a counter direction control circuit having an input line connected to said output line of said BEMF generating circuit and an output line connected to said count direction control terminal of said counter circuit;

wherein upon startup of said spin motor, said counter direction control circuit generates a signal having a first level on said output line so that said count value of said counter circuit changes value in a first direction in response to each clock pulse generated on said output line by said logic circuit; and

in response to said BEMF commutation pulse, said counter direction control circuit generates a signal having a second level to said count direction control terminal of said counter circuit so that said count value changes in a second direction different from said first direction.

11. The startup control circuit as recited in claim 10 wherein said counter circuit further comprises:

a count value bus wherein said count value bus carries a signal representing said count value; and

a count detector connected to said count value bus and to said counter circuit output line wherein said count detector generates said startup pulse upon detection of a selected count value.

12. The startup control circuit as recited in claim 10, said counter circuit further comprising:

a count value bus wherein said count value bus carries a signal representing said count value; and

a count detector having an input line connected to said count value bus and an output line connected to said logic circuit;

wherein said count detector generates a signal on said output line upon detection of a selected count value; and

said logic circuit, in response to a count detector output signal, inhibits generation of signals on said output line of said logic circuit.

13. The startup control circuit as recited in claim 12 further comprising a sequencer circuit having an input line coupled to said counter circuit output line wherein said sequencer circuit commutates a phase of said spin motor in response to said startup pulse from said counter circuit.

14. The startup control circuit as recited in claim 13 further comprising a first pulse generator circuit having (i) an input line connected to the output line of said BEMF generating circuit and (ii) an output line coupled to said sequencer circuit wherein in response to said BEMF commutation pulse, said first pulse generator circuit generates a pulse on said output line.

15. The startup control circuit as recited in claim 14 wherein said counter direction control circuit comprises a second pulse generator circuit having (i) an input line connected to the output line of said BEMF generating circuit and (ii) an output line connected to said count direction control terminal of said counter circuit wherein said input line and said output line of second pulse generator circuit are said input line and output line, respectively, of said counter direction control circuit.

16. The startup control circuit as recited in claim 10 wherein said counter circuit is programmable.

17. The startup control circuit as recited in claim 16 further comprising a microprocessor interface coupled to said counter circuit.