Serial processing circuits with serial chaining

• US 5,467,090 A
• Filed: 09/28/1994
• Issued: 11/14/1995
• Est. Priority Date: 04/30/1992
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Baumgartner, Richard A., Herleikson, Earl C., Moore, Charles E.
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US08/314,162
• Time in Patent Office: 412 Days
• Field of Search: 341/139, 341/141, 341/155
• US Class Current: 341/155
• CPC Class Codes: A61B 5/30 Input circuits therefor
• CPC Class Codes: A61B 5/305 Common mode rejection
• CPC Class Codes: A61B 5/7203 for noise prevention, reduction or removal
• CPC Class Codes: A61B 5/7242 using integration
• CPC Class Codes: G05B 19/042 using digital processors G05B19/05 takes precedence
• CPC Class Codes: G16H 40/40 for the management of medical equipment or devices, e.g. scheduling maintenance or upgrades
• CPC Class Codes: G16H 40/63 for local operation

Abstract

A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Claims

1. A signal processing system comprising:

a plurality of integrated circuits serially connected together in a chain, having a first integrated circuit in said chain and a last integrated circuit in said chain;

each said integrated circuit in said plurality of integrated circuits further comprising;

analog to digital converter means for converting a plurality of analog input signals into digital output data;

shift register means for;

receiving and storing said digital output dam, and for serially shifting digital data in from a serial input port, and for serially shifting data out through a serial output port; and

each integrated circuit in said plurality of integrated circuits, except said first integrated circuit, having its serial input port connected to the serial output port of a serially preceding integrated circuit.

2. A signal processing system as in claim 1 further comprising:

binary master/slave means, in each integrated circuit in said plurality of integrated circuits, for receiving a master/slave signal and for forcing each said integrated circuit to be a master or a slave in response to the master/slave signal, one of the integrated circuits being the master and the remaining integrated circuits being the slaves;

a dam clock port in each integrated circuit in said plurality of integrated circuits,

all said data clock ports being connected together, the data clock port for the master being a clock output port and the data clock port for each of the slaves being a clock input port, the master generating a dam clock signal at its data clock port.

3. A signal processing system as in claim 2 wherein each said integrated circuit further comprises:

synchronization means for receiving an external sync signal and for starting said analog to digital conversion means in response to said external sync signal.

4. A signal processing system as in claim 3 further comprising:

said external sync signal electrically coupled to a sync input port on the master.

5. A signal processing system as in claim 1 wherein each said integrated circuit further comprises:

a plurality of analog signal processing channels, each said signal processing channel having a plurality of digitally controllable functions; and

digital control means for controlling said plurality of digitally controllable functions in response to a digital command; and

a serial digital input control port for receiving said digital control commands.

6. A signal processing system as in claim 5 wherein said digital control commands further comprise a command address and wherein each integrated circuit in said plurality of integrated circuits further comprises:

address means for receiving an address signal and said digital control command and for enabling the integrated circuit containing said address means to respond to said control command only if said command address matches said address signal.

7. A signal processing system as in claim 5 further comprising:

a first optical coupler receiving said data output from said last integrated circuit and coupling said data output from said last integrated circuit to an external data receiving means; and

a second optical coupler receiving an external serial digital command signal and coupling said external serial digital command signal to each said serial digital input control port.

8. A signal processing system as in claim 1, each integrated circuit in the plurality of integrated circuits further comprising:

binary master/slave means for receiving a master/slave signal and for forcing each said integrated circuit to be a master or a slave in response to the master/slave signal;

a data clock port that is an output port for each said master and an input port for each slave;

synchronization means for receiving an external sync signal and for starting said analog to digital conversion means in response to said external sync signal;

a plurality of analog signal processing channels, each said signal processing channel having a plurality of digitally controllable functions;

digital control means for receiving a digital command and for controlling said plurality of digitally controllable functions in response to said digital command;

a serial digital input control port for receiving said digital control commands;

address means for receiving an address signal and said digital control command and for enabling the integrated circuit containing said address

means to respond to said control command only if said command address matches said address signal;

all said data clock ports being connected together; and

wherein said last integrated circuit is a master and each integrated circuit in said plurality of integrated circuits except said last integrated circuit is a slave.

9. A signal processing system as in claim 8 further comprising:

a first optical coupler receiving said output data from said last integrated circuit and coupling said output data from said last integrated circuit to an external data receiving means;

a second optical coupler receiving said data clock and coupling said data clock to said external data receiving means;

a third optical coupler receiving said external sync signal and coupling said external sync signal to a sync input signal on said last integrated circuit; and

a fourth optical coupler receiving an external digital command signal and for coupling said external serial digital command signal to each said serial digital input control port.

10. A process for serially connecting a plurality of integrated circuits into a chain;

wherein each said integrated circuit further comprises analog to digital converter means for converting a plurality of analog input signals into digital output data;

said process comprising the steps of;

(a) arranging said plurality of integrated circuits in a logically linear sequence having a first integrated circuit and a last integrated circuit;

(b) storing, within each integrated circuit, said digital output dam in a shift register;

(c) serially shifting, within each integrated circuit, digital data in from a serial input port into said shift register;

(d) serially shifting, within each integrated circuit, data out from said shift register through a serial output port;

(e) connecting said serial input port to the serial output port of a serially preceding integrated circuit for each integrated circuit in said plurality of integrated circuits, except said first integrated circuit;

(f) connecting said serial input port of said first integrated circuit to logical "zero";

(g) connecting said serial output port of said last integrated circuit to an external data receiving means; and

(h) periodically synchronously shifting serial digital data through each said integrated circuit until said logical "zero" from said input port on said first integrated circuit has shifted into said external data receiving means.

11. A signal processing system comprising:

a first integrated circuit having a first plurality of input nodes, a first output node, first signal conditioning circuitry switchably connected to the first input nodes and driving the first output node, first control circuitry receiving digital control signals, the first control circuitry selecting which of the first input nodes are switched to the first signal conditioning circuitry in response to the digital control signals;

a second integrated circuit having a second plurality of input nodes, a second output node, second signal conditioning circuitry switchably connected to the second input nodes and driving the second output node, second control circuitry receiving the digital control signals, the second control circuitry selecting which of the second input nodes are switched to the second signal conditioning circuitry in response to the digital control signals;

the first output node connected to one of the second input nodes; and

the second output node driven by the second signal conditioning circuitry in response to the selected first and second input nodes.

12. The signal processing system of claim 11 further comprising:

the first signal conditioning circuitry including a first shift register, the first shift register having a first shift register output connected to the first output node;

the second signal conditioning circuitry including a second shift register, the second shift register having a second shift register output connected to the second output node and a second shift register input connected to the one of the second input nodes that is connected to the first output node; and

the first shift register output thereby connected to the second shift register input.

13. The signal processing system of claim 12 further comprising:

the first signal conditioning circuitry including a first analog-to-digital converter, the first analog-to-digital converter having a first digital output connected to the first shift register;

the second signal conditioning circuitry including a second analog-to-digital converter, the second analog-to-digital converter having a second digital output connected to the second shift register; and

the second output node serially receiving the second digital output being shifted from the second shift register and the first digital output being shifted from the first shift register through the second shift register.

14. A process for converting multiple analog signals into a single digital signal, the process comprising the following steps:

(a) convening a first analog signal into first digital data in a first integrated circuit;

(b) storing the first digital data into a first shift register in the first integrated circuit;

(c) converting a second analog signal into second digital data in a second integrated circuit;

(d) storing the second digital data into a second shift register in the second integrated circuit;

(e) connecting an output of the first shift register to an input of the second shift register; and

(f) shifting data in both the first and second shift registers so that the second digital data in the second shift register is shifted out an output of the second register and the first digital data in the first shift register is shifted through the output of the first shift register and through the input of the second shift register and on through the output of the second shift register.