Semiconductor chip package and method of forming

• US 5,467,253 A
• Filed: 06/30/1994
• Issued: 11/14/1995
• Est. Priority Date: 06/30/1994
• Status: Expired due to Term

• Current Assignee: Consorzio Per La Ricerca Sulla, Freescale Semiconductor, Inc. (NXP Semiconductors NV), SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Geyer, Harry J., Heckman, James K., Carney, Francis J.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): WHANG, YOUNG
• Application Number:
  US08/269,241
• Time in Patent Office: 502 Days
• Field of Search: 361/761, 361/760, 361/777, 361/765, 361/767, 361/730, 361/736, 174/52.2, 174/260, 174/52.4, 174/261, 174/266, 174/264, 257/684, 257/678, 257/687, 257/693, 257/698, 257/787, 29/841, 29/848, 29/855, 29/856
• US Class Current: 361/761
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/1616 : Cavity shape
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: Y10T 29/49172 : by molding of insulating material

Abstract

A semiconductor device having a substrate support (22) and a method of forming the semiconductor device. A substrate (11) has conductive traces (12) and a bonding pad (13) on a bottom surface and conductive traces (14) and a semiconductor chip attach pad (17) on a top surface. The substrate support (22) has an aperture (23) and is coupled to the substrate (11). A semiconductor chip (31) is coupled to the semiconductor chip attach pad (17). The semiconductor chip (31) is covered by an encapsulating material (38) or a cap (41, 51) which provide protection for the semiconductor chip (31).

Claims

1. A semiconductor chip package, comprising:

a substrate having first and second surfaces, the first surface having at least one conductive trace disposed thereon and having a semiconductor chip receiving area, the second surface having at least one bonding pad disposed thereon, the at least one bonding pad coupled to the at least one conductive trace by a via; and

a substrate support coupled to the substrate, the substrate support providing structural strength for the substrate and having an aperture exposing the semiconductor chip receiving area, wherein the aperture cooperates with the substrate to form a cavity.

2. The semiconductor chip package of claim 1, wherein a semiconductor chip is coupled to the semiconductor chip receiving area.

3. The semiconductor chip package of claim 2, wherein an encapsulating material covers the semiconductor chip.

4. The semiconductor chip package of claim 2, wherein interconnect wires are bonded to the semiconductor chip and the cavity is covered with a metal cap having a portion that conforms to the shape of the interconnect wires and is electrically separated from the interconnect wires.

5. The semiconductor chip package of claim 1, wherein the cavity is covered by a cap.

6. The semiconductor chip package of claim 5, wherein a material of the cap is selected from the group consisting of ceramic, plastic, and metal.

7. The semiconductor chip package of claim 5, wherein a material of the cap is a bi-metal laminated cap comprising a layer of aluminum and a layer of iron.

8. The semiconductor chip package of claim 5, wherein the cavity contains a fluid.

9. The semiconductor chip package of claim 1, wherein a thickness of the substrate support ranges between approximately 125 microns and approximately 1,250 microns.

10. A semiconductor device package, comprising:

a substrate having top and bottom surfaces, wherein the top surface has a semiconductor chip attach pad and a conductive trace formed thereon and the bottom surface has a bonding pad formed thereon, and wherein a via couples the conductive trace to the bonding pad;

a semiconductor chip mounted to the semiconductor chip attach pad; and

a substrate support coupled to the top surface, wherein the substrate support has an aperture and provides structural strength for the substrate, the semiconductor chip exposed through the aperture and the aperture cooperating with the substrate to form a cavity.

11. The semiconductor device package of claim 10, wherein a solder ball is bonded to the bonding pad on the bottom surface.

12. The semiconductor device package of claim 10, wherein a cap covers the aperture.

13. The semiconductor device package of claim 10, wherein an encapsulating material fills the cavity.

14. A method for forming a semiconductor device package, comprising the steps of:

providing a substrate having first and second surfaces, the first surface having a die bonding area and at least one conductive trace disposed thereon and the second surface having at least one bonding pad disposed thereon, the at least one bonding pad coupled to the at least one conductive trace by a via; and

attaching a support to the substrate, the support having an aperture aligned to and exposing the die bonding area.

15. The method of claim 14, wherein the step of providing a substrate includes forming a patterned conductive layer on an insulating layer, the patterned conductive layer including the die bonding area.

16. The method of claim 14, wherein the step of providing a substrate includes providing the substrate having a thickness ranging between approximately 50 microns and approximately 1,500 microns.

17. The method of claim 16, wherein the step of attaching a support to the substrate includes attaching a planar support to the substrate, a material for the planar support selected from the group bismaleimidetriazine resin and FR-4.

18. The method of claim 14, wherein the step of attaching a support to the substrate includes coupling the substrate to the support with an adhesive material.

19. The method of claim 14, wherein the step of providing a substrate includes 19 mounting a semiconductor chip to the die bonding area.

20. The method of claim 19, wherein the step of attaching a support to the substrate includes covering the aperture with a cap.

21. The method of claim 19, wherein the step of attaching a support to the substrate includes covering the semiconductor chip with an encapsulation material.