Three-dimensional direct-write EEPROM arrays and fabrication methods

• US 5,467,305 A
• Filed: 03/12/1992
• Issued: 11/14/1995
• Est. Priority Date: 03/12/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Miyakawa, Makoto, Sakaue, Yoshinori, DiMaria, Donelli J.
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/850,734
• Time in Patent Office: 1,342 Days
• Field of Search: 365/195, 365/185, 365/149, 257/319, 257/320, 257/302, 257/298
• US Class Current: 365/185.08
• CPC Class Codes: H01L 29/7882 charging by injection of carriers through a conductive insulator, e.g. Poole-Frankel conduction
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

Claims

1. A direct-write EEPROM memory array formed in a semiconductor substrate, said memory array comprising:

a plurality of substantially parallel elongated trenches adjacently formed in the semiconductor substrate;

a plurality of vertical direct-write EEPROM cells disposed within said plurality of elongated trenches, multiple EEPROM cells being disposed within each of said plurality of elongated trenches, each of said multiple EEPROM cells disposed in each of said plurality of elongated trenches being paired with another of said EEPROM cells disposed in the same elongated trench such that EEPROM cell pairs are disposed in said plurality of elongated trenches, wherein said multiple EEPROM cells in each of said plurality of elongated trenches include a continuous polysilicon structure that functions as a recall gate for said multiple EEPROM cells in said trench, and each EEPROM cell includes an isolated polysilicon structure which functions as a floating gate for the cell;

a plurality of discrete control gates disposed within said plurality of elongated trenches, each control gate being shared by one of said EEPROM cell-pairs; and

an electrically continuous diffusion structure associated with at least one elongated trench of said plurality of elongated trenches, said electrically continuous diffusion structure comprising either a source node or a drain node for each of at least two EEPROM cells of said multiple EEPROM cells disposed in said at least one elongated trench of said plurality of elongated trenches.

2. The direct-write EEPROM memory array of claim 1, wherein each of said recall gates can function as an inhibit gate against the formation of a vertical channel in the substrate adjacent one of said floating gates associated with said recall gate, whereby only one of a pair of EEPROM cells sharing a common diffusion can be read or programmed by appropriately biasing an associated recall gate.

3. The direct-write EEPROM memory array of claim 2, wherein the threshold voltage of each floating gate (V_T1) is distinct from the threshold voltage of the associated recall gate (V_T2) such that the inhibit function of selected ones of said recall gates is enhanced.

4. The direct-write EEPROM memory array of claim 1, further comprising a plurality of interconnection lines disposed above and orthogonal to said plurality of elongated trenches, each of said plurality of interconnection lines being coupled to at least one of said plurality of discrete control gates disposed within said trenches.

5. The direct-write EEPROM memory array of claim 1, wherein said plurality of substantially parallel, elongated trenches comprise shallow trenches formed in said semiconductor substrate.

6. The direct-write EEPROM memory array of claim 5, wherein said polysilicon floating gates are disposed along opposite walls of said shallow trenches and are separated from said semiconductor substrate by a high dielectric material such that when a negative charge resides on one of said floating gates, the ability to form an inversion layer in said substrate adjacent said negatively charged floating gate is reduced.

7. The direct-write EEPROM memory array of claim 6, wherein said discrete polysilicon control gates are disposed vertically and parallel to said continuous recall gates in each of said trenches, said control gates and said associated recall gate in each trench being separated by a high dielectric material, and each of said recall gates being disposed along a bottom portion of one of said shallow elongated trenches.

8. The direct-write EEPROM memory array of claim 7, wherein said vertically disposed control gate and recall gate in each of said plurality of trenches are separated from the corresponding floating gate pairs by a material which permits Fowler-Nordheim electron tunneling.

9. The direct-write EEPROM memory array of claim 8, wherein said separation material permitting Fowler-Nordheim electron tunneling comprises a silicon rich dielectric.