Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms
First Claim
1. A method for increasing the threshold voltage of at least one of a plurality of floating-gate memory cells in a nonvolatile integrated-circuit memory having a substrate connected to a reference voltage each said memory cells being of the single-transistor, non-split-gate type, said method comprising:
- causing the voltage on the control gates of said plurality of memory cells to have a positive value with respect to said reference voltage;
causing the voltage on the sources of said plurality of memory cells to have a positive value with respect to said reference voltage; and
causing a current to flow into the drains of said plurality of memory cells;
said voltage on the control gates having a value less than the typical threshold voltage of said plurality of cells with said voltage on said sources of said plurality of cells.
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Accused Products
Abstract
The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11 ) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.
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Citations
19 Claims
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1. A method for increasing the threshold voltage of at least one of a plurality of floating-gate memory cells in a nonvolatile integrated-circuit memory having a substrate connected to a reference voltage each said memory cells being of the single-transistor, non-split-gate type, said method comprising:
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causing the voltage on the control gates of said plurality of memory cells to have a positive value with respect to said reference voltage; causing the voltage on the sources of said plurality of memory cells to have a positive value with respect to said reference voltage; and causing a current to flow into the drains of said plurality of memory cells; said voltage on the control gates having a value less than the typical threshold voltage of said plurality of cells with said voltage on said sources of said plurality of cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for increasing the threshold voltage of at least one of a plurality of floating-gate memory cells in a nonvolatile integrated-circuit memory having a substrate, each said memory cell being of the single-transistor, non-split-gate type, said method comprising:
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causing the voltage on the control gates of said memory cells to have a positive value with respect to the voltage on said substrate; reverse-biasing the sources of said memory cells with respect to said substrate; reverse biasing the drains of said memory cells with respect to said substrate; and allowing a current to flow between said drains and said sources of at least some of said plurality of cells; said voltage on the control gates having a value less than the typical threshold voltage of said plurality of memory cells with said sources reverse-biased. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification