Tamper-proof data storage

• US 5,467,396 A
• Filed: 10/27/1993
• Issued: 11/14/1995
• Est. Priority Date: 10/27/1993
• Status: Expired due to Fees

• Current Assignee: Titan (L3Harris Technologies, Inc.)
• Original Assignee: Titan (L3Harris Technologies, Inc.)
• Inventors: Reiner, Thomas C., Schossow, Stephen R.
• Primary Examiner(s): Barron, Jr., Gilberto
• Application Number:
  US08/144,052
• Time in Patent Office: 748 Days
• Field of Search: 380/3, 380/4, 364/246.9, 364/969.3
• US Class Current: 713/193
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories

Abstract

In a data processing system, stored data that is essential to a given data processing operation, such encryptographic key generation, is tamper proof in that if such data is altered, processing of the altered data is inhibited upon retrieval. The system includes a memory for storing a plurality of data bits and in which the storage of one type of the bits is irreversible; a data processor, such as a cryptographic processor, coupled to the memory for retrieving the bits from a first section of the memory and for processing the retrieved bits with other data bits; an authentication unit coupled to the memory for processing the bits stored in the first section of the memory with bits stored in a second section of the memory to provide an indication as to whether or not the bits stored in the first section of the memory have a predetermined relationship to the bits stored in the second section of the memory; and a gate coupled to the data processor and to the authentication unit for inhibiting the data processor from processing the data bits retrieved from the first section of the memory unless the authentication unit indicates that the bits stored in the first section of the memory have the predetermined relationship to the bits stored in the second section of the memory. Since storage of one type of the bits is irreversible, although a pirate can alter the logic state of one type of bit in one section of the memory, he cannot alter the the logic state of the other type of bit in the other of the memory so as restore the predetermined relationship between the bits in the first section of the memory and the bits in the second section of the memory.

Claims

1. A data processing system in which processing of retrieved altered data is inhibited, comprising

a memory for storing a plurality of data bits and in which the storage of one type of said bits is irreversible;

a data processor coupled to the memory for retrieving said bits from a first section of the memory and for processing the retrieved bits with other data bits;

authentication means coupled to the memory for processing the bits stored in the first section of the memory with bits stored in a second section of the memory to provide an indication as to whether or not the bits stored in the first section of the memory have a predetermined relationship to the bits stored in the second section of the memory; and

a gate coupled to the data processor and to the authentication processing means for inhibiting the data processor from processing the data bits retrieved from the first section of the memory unless the authentication means indicate that the bits stored in the first section of the memory have said predetermined relationship to the bits stored in the second section of the memory.

2. A system according to claim 1, wherein the data processor is a cryptographic processor that generates a cryptographic key in response to the data bits retrieved from the first section of the memory.

3. A system according to claim 1, wherein said predetermined relationship is that the bits stored in the first section of the memory are the binary complement of the bits stored in the second section of the memory.

4. A system according to claim 3, wherein the processing means comprise

a logic array coupled to the memory for separately comparing each of the bits stored in the first section of the memory with the bits stored in respectively corresponding bit positions of the second section of the memory and for indicating whether any of said compared pairs of bits are the same;

and

wherein the gate is coupled to the data processor and the logic array for inhibiting the data processor from processing the data bits retrieved from the first section of the memory when the logic array indicates that any of said compared pairs of bits are the same.

5. A system according to claim 4, wherein the data processor is a cryptographic processor that generates a cryptographic key in response to the data bits retrieved from the first section of the memory.

6. A system according to claim 3, wherein the authentication means comprises

a counter coupled to the memory for counting the total number of either one type or the other type of the bits stored in both the first section and the second section of the memory;

and

means coupled to the counter for comparing said count to the number of bits stored in the first section of the memory to provide an indication as to whether or not said count equals the number of bits stored in the first section of the memory; and

wherein the gate is coupled to the data processor and the comparing means for inhibiting the data processor from processing the data bits retrieved from the first section of the memory when the comparing means indicate that said count does not equal the number of bits stored in the first section of the memory.

7. A system according to claim 6, wherein the data processor is a cryptographic processor that generates a cryptographic key in response to the data bits retrieved from the first section of the memory.

8. A system according to claim 1, wherein said predetermined relationship is that the binary value of the bits stored in the second section of the memory is equal to the number of either one type or the other type of the bits stored in the first section of the memory.

9. A system according to claim 8, wherein the processing means comprise

a counter coupled to the memory for counting either the number of one type or the number of the other type of said bits stored in the first section of the memory;

and

means coupled to the counter and the memory for comparing said count with a value stored in a second section of the memory to provide an indication as to whether or not said count equals said stored value; and

wherein the gate is coupled to the data processor and the comparing means for inhibiting the data processor from processing the data bits retrieved from the first section of the memory when the comparing means indicate that said count does not equal said stored value.

10. A system according to claim 9,

wherein the counter is coupled to the memory for storing said count in the second section of the memory as said stored value when data bits are initially stored in the first section of the memory.

11. A system according to claim 9, wherein the data processor is a cryptographic processor that generates a cryptographic key in response to the data bits retrieved from the first section of the memory.