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Adaptive clock skew and duty cycle compensation for a serial data bus

  • US 5,467,464 A
  • Filed: 03/09/1993
  • Issued: 11/14/1995
  • Est. Priority Date: 03/09/1993
  • Status: Expired due to Term
First Claim
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1. A double-edge de-skewer apparatus for reducing skew between a clock signal and a data signal having a leading edge and a trailing edge, received along first and second communication lines, said apparatus comprising:

  • a delay line coupled to receive said clock signal from said first communication line for delaying said clock signal to generate a plurality of delayed clock signals;

    a first detector coupled to receive said plurality of delayed clock signals from said delay line and said data signal from said second communication line, for comparing the delayed clock signals with said leading edge of the data signal to identify a first delayed clock signal having a least amount of skew with respect to said data signal leading edge; and

    a second detector coupled to said delay line and said second communication line for comparing the delayed clock signals with said trailing edge of the data signal to identify a second delayed clock signal having a least amount of skew with respect to said data signal trailing edge;

    a first output coupled to said first detector for outputting said first delayed clock signal; and

    a second output coupled to said second detector for outputting said second delayed clock signal.

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