Adaptive clock skew and duty cycle compensation for a serial data bus

• US 5,467,464 A
• Filed: 03/09/1993
• Issued: 11/14/1995
• Est. Priority Date: 03/09/1993
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Oprescu, Florin, Van Brunt, Roger
• Primary Examiner(s): Kriess, Kevin A.
• Application Number:
  US08/028,387
• Time in Patent Office: 980 Days
• Field of Search: 395/550
• US Class Current: 713/400
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: H04L 7/044 using a single bit, e.g. start stop bit

Abstract

The de-skewer utilizes a delay line to generate a set of delayed versions of an input clock signal. A bank of flip-flops compares pulses within the delayed clock signals to a synchronization pulse provided within an input data signal. A detector receives outputs from the flip-flops and selects the delayed clock signal having the least amount of skew based on the values of the output from the flip-flops. A multiplexer outputs the selected delayed clock. The de-skewer provides a simple, open-loop circuit for eliminating skew between parallel transmission paths. The de-skewer is ideally suited for eliminating skew from sources which do not vary significantly as a function of time. In particular, the de-skewer is well-suited for use in a data transmission system providing short bursts of high data rate transmissions. A double-edged de-skewer is also described which is capable of generating a pair of clock signals for use in eliminating duty cycle distortion.

Claims

1. A double-edge de-skewer apparatus for reducing skew between a clock signal and a data signal having a leading edge and a trailing edge, received along first and second communication lines, said apparatus comprising:

a delay line coupled to receive said clock signal from said first communication line for delaying said clock signal to generate a plurality of delayed clock signals;

a first detector coupled to receive said plurality of delayed clock signals from said delay line and said data signal from said second communication line, for comparing the delayed clock signals with said leading edge of the data signal to identify a first delayed clock signal having a least amount of skew with respect to said data signal leading edge; and

a second detector coupled to said delay line and said second communication line for comparing the delayed clock signals with said trailing edge of the data signal to identify a second delayed clock signal having a least amount of skew with respect to said data signal trailing edge;

a first output coupled to said first detector for outputting said first delayed clock signal; and

a second output coupled to said second detector for outputting said second delayed clock signal.

2. A double-edged de-skewer apparatus for reducing skew between a clock signal and a data signal, said apparatus comprising:

a first input for receiving a clock signal;

a second input for receiving a data signal, said data signal having a leading signal edge and a trailing signal edge;

a delay line coupled to receive said clock signal from said first input for delaying said clock signal so as to generate a plurality of delayed clock signals; and

a detector coupled to said second input and said delay line for comparing said plurality of delayed clock signals with said data signal to identify a first delayed clock signal having a least amount of skew relative to the leading signal edge of said data signal, and to identify a second delayed clock signal having a least amount of skew relative to the trailing signal edge of said data signal.

3. The apparatus of claim 2, wherein said data signal is preceded by first and second preamble portions, each portion having leading and trailing signal edges separated by a single clock cycle, and wherein said detector means compares said plurality of delayed clock signals to said first preamble portion to identify said first delayed clock signal, and said detector means compares said plurality of delayed clock signals to said second preamble portion to identify said second delayed clock signal.

4. A double-edge de-skewer apparatus for reducing skew in a communication channel having first and second communication lines, said apparatus comprising:

a first input for receiving a clock signal along a first communication line;

a second input for receiving a data signal along a second communication line, wherein data received along said second communication line is skewed with respect to the clock signal received along said first communication line, said data signal having first and second preambles each providing a leading signal edge and a trailing signal edge separated by a single clock cycle;

a plurality of sequentially connected delay elements connected to said first communication line, each delay element providing a respective delayed clock signal, whereby said clock signal is delayed by increasing amounts as said clock signal is transmitted through said sequentially arranged delay elements;

a detector, connected to said delay elements, for identifying a delay element providing a delayed clock signal having a least amount of skew with respect to a signal edge of said data signal;

a controller for controlling operation of said detector to identify a first de-skewed signal comprising an output of a first said delay element having a least amount of skew relative to the leading signal edge in said first preamble and a second de-skewed signal comprising an output of a second said delay element having a least amount of skew relative to the trailing signal edge in said second preamble;

a first multiplexer, having inputs connected to said delay line elements, to said controller means and to said detector circuit for outputting said first de-skewed signal; and

a second multiplexer, having inputs connected to said delay line elements, to said controller means, and to said detector circuit for outputting said second de-skewed signal.

5. The double-edged de-skewer of claim 4, further including:

inverter elements coupled to respective said delay elements for providing inverted delayed clock signals output from each of said delay elements;

a clock multiplexer, connected to said delay elements, to outputs of said inverter elements, and to said controller for outputting delayed clock signals corresponding to said first preamble and for outputting inverted delayed clock signals corresponding to said second preamble.

6. The double-edged de-skewer of claim 4, wherein said detector means includes:

a plurality of flip-flop circuits operably connected between said delay elements and said detector, each said flip-flop circuit having a first input connected to an output of a respective delay element, and a second input coupled to receive said data signal from said second communication line.

7. An apparatus for reducing skew in a communication channel having first and second communication lines, said apparatus comprising:

a first input coupled to receive a first signal along said first communication line, said first signal including a clock pulse having a leading edge and a trailing edge;

a second input coupled to receive a second signal along said second communication line, said second signal including a synchronization pulse having a leading edge and a trailing edge;

a delay line coupled to said first input for delaying said first signal so as to generate a plurality of delayed signals each including a clock pulse having a leading edge and a trailing edge corresponding to but delayed by a respective amount from the clock pulse of said first signal;

a comparator coupled to said second input and said delay line, for comparing said delayed signals with said second signal to identify a said delayed signal having a least amount of skew with respect to said second signal by determining, at the leading edge of the clock pulse of each said delayed signal, whether said synchronization pulse of said second signal is between the leading and trailing edges of that clock pulse; and

an output selector outputting a clock signal synchronized with the clock pulse of the delayed signal identified by the comparator, said output selector being coupled to said comparator.

8. An apparatus as claimed in claim 7, wherein:

said delay line comprises a plurality of sequentially connected delay elements coupled to said first communication line, each delay element providing a delay to said first signal, whereby said first signal is delayed by increasing amounts as said first signal is transmitted through said sequentially connected delay elements, each said delayed signal being provided from the output of a respective said delay element; and

said comparator comprises;

a plurality of edge-triggered flip-flop circuits, each having a clocking input coupled to receive a respective said delayed signal from said delay line, and a data input coupled to receive said second signal; and

a detector circuit coupled to receive output signals from said plurality of flip-flops for determining, on the basis of said output signals, the output of which delay element provides the delayed signal having the least amount of skew.

9. An apparatus as claimed in claim 8, wherein said output selector includes a multiplexer coupled to receive said plurality of delayed signals for outputting as said clock signal said delayed signal having the least amount of skew identified by said comparator.

10. An apparatus for reducing skew in a communication channel having first and second communication lines, said apparatus comprising:

a first input receiving a first signal along said first communication line, said first signal including a clock pulse having a leading edge and a trailing edge;

a second input receiving a second signal along said second communication line, said second signal including a synchronization pulse having a leading edge and a trailing edge;

a delay line delaying said first signal so as to generate a plurality of delayed signals each including a clock pulse having a leading edge and a trailing edge corresponding to but delayed by a respective amount from the clock pulse of said first signal, wherein said delay line comprises a plurality of sequentially connected delay elements coupled to said first input, each delay element providing a delay to said first signal, whereby said first signal is delayed by increasing amounts as said first signal is transmitted through said sequentially connected delay elements, each said delayed signal being provided from the output of a respective said delay element;

a comparator comparing said delayed signals with said second signal to identify a said delayed signal having a least amount of skew with respect to said second signal by determining, at the leading edge of the clock pulse of each said delayed signal, whether said synchronization pulse of said second signal is between the leading and trailing edges of that clock pulse, said comparator comprising;

a plurality of edge-triggered flip-flop circuits, each having a clocking input coupled to receive a respective said delayed signal from said delay line, and a data input coupled to receive said second signal from said second input, wherein each flip-flop circuit outputs a first output value if the leading edge of the pulse of the respective delayed signal occurs between the leading and trailing edges of the pulse of said second signal, and outputs a second value otherwise, the outputs of the flip-flop circuits providing a sequence of said first output values; and

a detector coupled to receive the outputs of said plurality of flip-flops for determining the delayed signal having the least amount skew by determining the delayed signal corresponding to the flip-flop circuit which provides a median value of said sequence of first output values; and

an output selector outputting a clock signal synchronized with the clock pulse of the delayed signal identified by the comparator.

11. An apparatus as claimed in claim 10, wherein said output selector includes a multiplexer coupled to receive said plurality of delayed signals and outputting as said synchronized clock signal said delayed signal having the least amount of skew determined by said detector.

12. An apparatus as claimed in claim 11, wherein said first output value corresponds to a logical value of 1 and said second output value corresponds to a logical value of 0.

13. An apparatus as claimed in claim 12, wherein said plurality of flip-flops includes N flip-flops and wherein an amount of delay provided by each said delay element is selected to ensure that no more than N=2 flip-flops outputs said first output value.

14. An apparatus for reducing skew in a communication channel having at least two communication lines, said apparatus comprising:

a first input for receiving a clock signal along a first communication line;

a second input for receiving a data signal along a second communication line, said data signal having a preamble providing a synchronization pulse having a leading edge and a trailing edge separated by a single clock cycle;

a plurality of sequentially connected delay elements coupled to said first input, each delay element providing a certain delay to said clock signal, whereby said clock signal is delayed by increasing amounts as it is transmitted through said sequentially arranged delay elements;

a plurality of primary flip-flop circuits, each having a clocking input coupled to receive output from a respective said delay element and a data input coupled to receive said data signal from said second input;

a plurality of secondary flip-flop circuits, each having a clocking input coupled to receive output from a respective said delay element and a data input coupled to receive output from a respective corresponding primary flip-flop circuit;

a detector circuit which receives an output of each secondary flip-flop circuit, wherein each said secondary flip-flop circuit outputs a first logic value to said detector circuit if a leading edge of the clock signal at the output of the corresponding respective delay element occurs between said leading and trailing edges of said synchronization pulse, and outputs a second logic value otherwise, said detector circuit including selection circuitry for selecting the output of one of said secondary flip-flop circuits which outputs said first logic value and providing a selection signal; and

a multiplexer coupled to receive the output of each said delay element and said selection signal so as to output a delayed clock signal from one of said delay elements on the basis of said selection signal.

15. An apparatus for reducing skew as claimed in claim 14, wherein said delay elements and said primary flip-flop circuits are selected such that:

space="preserve" listing-type="equation">T.sub.d max ≧

(T.sub.clock +T.sub.s max +T.sub.h max)/3; and

space="preserve" listing-type="equation">T.sub.d min ≧

T.sub.clock /(n+1);

where

T_d max =a worst case maximum delay for any said delay element

T_d min =a worst case minimum delay for any said delay element

n=the number of sequentially connected delay elements

T_s max =a worst case maximum set-up time for any said primary flip-flop circuit

T_h max =a worst case maximum hold time for any said primary flip-flop circuit

T_clock =a clock period.

16. A method for reducing skew in a communication channel having first and second communication lines, comprising the steps of:

receiving a first signal along said first communication line, said first signal including a clock pulse having a leading edge and a trailing edge;

receiving a second signal along said second communication line, said second signal including a synchronization pulse having a leading edge and a trailing edge;

successively delaying said first signal to generate a plurality of delayed signals each including a clock pulse having a leading edge and a trailing edge corresponding to but delayed by a respective amount from the clock pulse of said first signal;

comparing said delayed signals with said second signal to identify a said delayed signal having a least amount of skew with respect to said second signal by determining, at the leading edge of the clock pulse of each said delayed signal, whether said synchronization pulse of said second signal is between the leading and trailing edges of that clock pulse, said comparison providing a sequence of said first output values;

selecting one of said plurality of delayed signals which corresponds to a median value of said sequence of first output values; and

outputting the selected one of said plurality of delayed signals as a clock signal having reduced skew with respect to said second signal.