Method of making power VFET device
First Claim
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1. A method of forming a vertical transistor device comprising:
- a. forming a n-type first drain/source layer over a substrate;
b. patterning a top portion of said first drain/source layer to form a channel and a trench, wherein said trench is formed where said first drain/source layer is removed after patterning and said channel is formed adjacent to said trench in said top portion of said first drain/source layer that is not removed during patterning;
c. forming a p-type carbon doped gate structure in said trench; and
d. forming a n-type second drain/source layer over said gate structure and said channel.
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Abstract
This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44. Other devices and methods are also disclosed.
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9 Claims
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1. A method of forming a vertical transistor device comprising:
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a. forming a n-type first drain/source layer over a substrate; b. patterning a top portion of said first drain/source layer to form a channel and a trench, wherein said trench is formed where said first drain/source layer is removed after patterning and said channel is formed adjacent to said trench in said top portion of said first drain/source layer that is not removed during patterning; c. forming a p-type carbon doped gate structure in said trench; and d. forming a n-type second drain/source layer over said gate structure and said channel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification