Method of making power VFET device

• US 5,468,661 A
• Filed: 06/17/1993
• Issued: 11/21/1995
• Est. Priority Date: 06/17/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kim, Tae S., Yang, Jau-Yuann, Yuan, Han-Tzong, Plumton, Donald L.
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US08/078,388
• Time in Patent Office: 887 Days
• Field of Search: 437/184, 437/203, 437/40, 437/41, 437/176, 437/911, 437/49, 148/DIG. 126
• US Class Current: 438/193
• CPC Class Codes: H01L 29/66454 Static induction transistors [SIT], e.g. permeable base transistors [PBT]
• CPC Class Codes: H01L 29/66924 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44. Other devices and methods are also disclosed.

Claims

1. A method of forming a vertical transistor device comprising:

a. forming a n-type first drain/source layer over a substrate;

b. patterning a top portion of said first drain/source layer to form a channel and a trench, wherein said trench is formed where said first drain/source layer is removed after patterning and said channel is formed adjacent to said trench in said top portion of said first drain/source layer that is not removed during patterning;

c. forming a p-type carbon doped gate structure in said trench; and

d. forming a n-type second drain/source layer over said gate structure and said channel.

2. The method of claim 1, wherein said first drain/source layer is formed on a n+ substrate.

3. The method of claim 1, wherein a cap layer is formed over said second drain/source layer.

4. The method of claim 3, wherein said cap layer has n+ doping.

5. The method of claim 1, wherein said first drain/source layer, said gate structure, and said second drain/source layer are GaAs.

6. The method of claim 1, wherein said first drain/source layer, said gate structure, and said second drain/source layer are epitaxially formed.

7. The method of claim 1, wherein said channel and said trench are formed by a dry etch process.

8. The method of claim 1, wherein said gate structure is selectively grown.

9. The method of claim 8, wherein said gate structure is epitaxially grown such that said gate structure grows faster laterally than vertically.