Method of fabricating three-dimensional direct-write EEPROM arrays

• US 5,468,663 A
• Filed: 03/16/1995
• Issued: 11/21/1995
• Est. Priority Date: 03/12/1992
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Miyakawa, Makoto, Sakaue, Yoshinori, DiMaria, Donelli J.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/405,128
• Time in Patent Office: 250 Days
• Field of Search: 437/43, 437/48, 437/203, 437/915, 148/DIG. 50
• US Class Current: 438/259
• CPC Class Codes: H01L 29/7882 charging by injection of carriers through a conductive insulator, e.g. Poole-Frankel conduction
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

Claims

1. A method for fabricating a semiconductor device memory array, said method comprising the steps of:

(a) providing a substrate of a first conductivity type material and having a first surface, said substrate including a buried plate region having a higher concentration of said first conductivity type material and a well region of a second conductivity type material, said well region extending from said first surface of said substrate to said buried plate region of said substrate, said substrate further including a diffusion region of said first conductivity type material extending from said first surface partially into said well region of said second conductivity type material;

(b) forming a trench mask on said first surface of said substrate, said trench mask exposing said first surface of said substrate through an elongated opening, said elongated opening being aligned over said first surface of said substrate such that said diffusion region of first conductivity type material is at least partially disposed under said trench mask adjacent said elongated opening in said mask;

(c) etching through said elongated mask opening to form a trench in said semiconductor substrate, said trench extending through said well region of second conductivity type material to said buried plate region of first conductivity type material;

(d) forming a polysilicon structure in a bottom portion of said substrate trench as a base for a recall gate;

(e) forming in said trench at least two sidewall floating gates having top and side surfaces, the top surface of each of said floating gates substantially overlapping said diffusion region of first conductivity type material disposed within said well region of second conductivity type material;

(f) depositing a spacer layer on the exposed side surfaces of said floating gates;

(g) forming a polysilicon extension of said recall gate partially up said spacer layer on said side surfaces of said floating gates; and

(h) forming at least one polysilicon program gate in said trench above said recall gate extension, said at least one program gate being disposed in an upper portion of said elongated trench and extending partially down said spacer layer on said side surfaces of said floating gates.

2. The fabrication method of claim 1, wherein said providing step (a) includes:

(i) providing a substrate of a first conductivity type material having a first surface, said substrate including said buried plate region of higher concentration of said first conductivity type material;

(ii) defining from said first surface of said substrate said well region of a second conductivity type material, said well region of second conductivity type material extending to said buried plate region in said substrate;

(iii) forming a diffusion mask on said first surface of said substrate, said diffusion mask including at least one elongated opening; and

(iv) ion implanting through said diffusion mask said exposed well region with material of the first conductivity type so as to create a high impurity density first conductivity type implant in said well region of second conductivity type material adjacent said first surface of said semiconductor substrate.

3. The fabrication method of claim 1, wherein said trench mask forming step (b) includes forming a non-erodible trench mask on said first surface of said substrate.

4. The fabrication method of claim 1, wherein said polysilicon structure forming step (d) includes the steps of:

(i) oxidizing exposed silicon in said trench to form a silicon oxide coating;

(ii) depositing polysilicon to fill said trench and recessing said polysilicon in said trench to provide a base of said recall gate; and

(iii) providing a uniform layer of silicon oxide on all exposed silicon.

5. The fabrication method of claim 1, wherein multiple sidewall floating gates are provided in said trench, and wherein said floating gate forming step (e) includes the steps of:

(i) depositing a polysilicon layer and recessing said polysilicon layer back to form two continuous sidewall floating gates having top and side surfaces, said top surfaces substantially overlapping said high impurity region of said first conductivity type material implanted into said well region of second conductivity type material; and

(ii) severing said continuous floating gate polysilicon layers along a series of parallel lines orthogonal to said elongated trench to form a series of discontinuous polysilicon floating gates in said trench.

6. The fabrication method of claim 1, wherein said spacer layer deposited in said step (f) comprises a silicon rich dielectric.

7. The fabrication method of claim 1, wherein said method further includes oxidizing a top surface of said recall gate polysilicon prior to formation of said polysilicon program gate above said recall gate.

8. The fabrication method of claim 1, further comprising the steps of oxidizing an upper surface of said program gates;

and stripping said trench mask from said first surface of said substrate.

9. The fabrication method of claim 1, wherein:

said step (b) includes forming a trench mask on said first surface of said substrate so as to expose said first surface of said substrate through a plurality of elongated openings, each of said elongated openings being aligned over said first surface of said substrate such that said diffusion region of first conductivity type material is at least partially disposed under said trench mask adjacent each of said elongated openings in the mask; and

said step (c) includes etching through said plurality of elongated mask openings to form a plurality of elongated trenches in said semiconductor substrate.

10. The fabrication method of claim 1, wherein said first conductivity type material comprises an N-type semiconductive material and said second conductivity type material comprises a P-type semiconductive material.