Method of forming MOS-gated semiconductor devices having mesh geometry pattern

• US 5,468,668 A
• Filed: 01/04/1995
• Issued: 11/21/1995
• Est. Priority Date: 11/29/1993
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Temple, Victor A. K., Neilson, John M. S., Jones, Frederick P., Wheatley, Carl F. Jr.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/368,612
• Time in Patent Office: 321 Days
• Field of Search: 437/47, 437/51, 437/56, 437/913, 437/48, 437/50, 148/DIG. 126
• US Class Current: 438/133
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 148/126 Power FETs

Abstract

A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device'"'"'s current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.

Claims

1. A method of making a MOS-gated semiconductor device comprising the steps of:

a. growing an epitaxial layer of a first conductivity type on a substrate of either the first or a second conductivity type;

b. doping a body region of the second conductivity type in a mesh pattern in the epitaxial layer so that the body region forms ribbons extending from nodes in the mesh pattern;

c. doping source contact regions of the second conductivity type into the body region at the nodes of the mesh pattern; and

d. doping source regions of the first conductivity type in the body region to a depth less than the depth of the body region so as to form channel regions of the first conductivity type on both sides of the source regions.

2. The method of claim 1 wherein the nodes are generally linear and the ribbons extend perpendicularly therefrom.

3. The method of claim 1 wherein the ribbons extend radially from the nodes.

4. The method of claim 3 wherein the ribbons extend at about 60°

to each other.

5. The method of claim 3 wherein the ribbons extend at about 90°

to each other.

6. A method of making a MOS-gated semiconductor device comprising the steps of:

(a) providing a surface layer of a first conductivity type on a substrate of either the first or a second conductivity type;

(b) providing a mesh pattern of ribbons that each extend from a source contact region of a first conductivity type in the surface layer of the device, each of the ribbons having a single source region of a second conductivity type between two channel regions of the first conductivity type connected beneath the source region by a body region of the first conductivity type; and

(c) providing a neck region of the second conductivity type between each of the ribbons.

7. The method of claim 6 wherein the source contact region is at a node of the mesh pattern.

8. The method of claim 7 wherein the ribbons extend radially from the source contact region.

9. The method of claim 6 wherein the source contact region is linear and the ribbons extend generally perpendicular therefrom.

10. The method of claim 6 wherein the surface layer is provided by growing an epitaxial layer.