Trenched DMOS transistor with channel block at cell trench corners

• US 5,468,982 A
• Filed: 06/03/1994
• Issued: 11/21/1995
• Est. Priority Date: 06/03/1994
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, Ho, Yueh-Se, Owyang, King, Chang, Mike F., Kwan, Sze-Hon, Van Der Linde, Jan
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/253,527
• Time in Patent Office: 536 Days
• Field of Search: 257/330, 257/331, 257/332, 257/341, 257/401, 257/520, 257/622, 437/48, 437/66, 437/67, 437/78, 437/79, 437/225, 437/913
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched DMOS transistor has improved device performance and production yield. During fabrication the cell trench corners, i.e. the areas where two trenches intersect, are covered on the principal surface of the integrated circuit substrate with a blocking photoresist layer during the source region implant step in order to prevent (block) a channel from forming in these corner areas. Punch-through is thereby eliminated and reliability improved, while source/drain on-resistance is only slightly increased. The blocking of the trench corners creates a cutout structure at each trench corner, whereby the source region does not extend to the trench corner, but instead the underlying oppositely-doped body region extends to the trench corner.

Claims

1. A trenched transistor cell comprising:

a substrate of a first conductivity type and defining at least two intersecting trenches;

an insulating layer lining the trenches;

a conductive material filling the trenches;

a source region of the first conductivity type and extending from a principal surface of the substrate adjacent to the trenches into the substrate; and

a body region of a second conductivity type opposite the first type and extending from the principal surface adjacent to the trenches into the substrate;

wherein at a corner of the cell defined by the two intersecting trenches, the source region is spaced apart from the trenches.

2. The cell of claim 1, wherein the source region is spaced apart from the corner of the cell by at least 0.1 microns and at the corner of the cell the body region is in contact with the trenches.

3. The cell of claim 1, wherein the cell includes at least four corners each defined by two intersecting trenches, and the source region is spaced apart from each corner of the cell.

4. The cell of claim 1, wherein a width of the trench is less than about 1.5 microns.

5. The cell of claim 1, wherein the body region extends into the substrate less than about 1.5 microns.

6. The cell of claim 1, wherein the source region extends into the substrate less than about 0.5 microns.

7. The cell of claim 2, wherein at the corner of the cell, the source region is not in contact with the trenches.

8. The cell of claim 1, further comprising an additional body region of the second conductivity type and extending from the principal surface at a central portion of the source region into the substrate, to a depth different than that of the body region.

9. The cell of claim 2, wherein at the principal surface the body region defines a rectangular area in contact with the trenches.

10. The cell of claim 1, further comprising a plurality of similar cells arranged in rows, and including a gate finger connecting the conductive material filling the trench in each row, and wherein a row of the cells adjacent the gate finger is inactive.

11. The cell of claim 1, wherein at a side of the cell away from the corner of the cell and defined by one of the trenches, the source region is adjacent that one of the trenches.

12. A trenched transistor cell comprising:

a substrate of a first conductivity type and defining at least two intersecting trenches;

an insulating layer lining the trenches;

a conductive material filling the trenches;

a source region of the first conductivity type and extending from a principal surface of the substrate adjacent to the trenches into the substrate; and

a body region of a second conductivity type opposite the first type and extending from the principal surface adjacent to the trenches into the substrate;

wherein at a corner of the cell defined by the two intersecting trenches, the source region is spaced apart from both of the trenches, and at a side of the cell away from the corner of the cell, the source region is adjacent one of the trenches.

13. A method of forming a transistor cell comprising:

providing a semiconductor substrate having a first region of a first conductivity type extending from a principal surface of the substrate;

forming at least two trenches in the substrate and extending into the substrate from the principal surface, the trenches intersecting to define a corner of the cell;

forming an insulating layer lining the trenches;

forming a conductive electrode in the trenches overlying the insulating layer;

forming a body region in the substrate having a second conductivity type, the body region extending into the substrate alongside the at least two trenches;

forming a masking layer over the principal surface and covering the principal surface at the corner; and

forming a source region of the first conductivity type and extending into the substrate from the principal surface alongside the at least two trenches, an extent of the source region being defined by the masking layer, the source region thereby being spaced apart from the corner.

14. The method of claim 13, wherein the step of forming semiconductor regions comprises implanting ions in the substrate.

15. The method of claim 13, wherein the step of forming semiconductor regions comprises pre-depositing dopant in the substrate.

16. The method of claim 13, wherein the step of forming the insulating layer comprises the steps of:

growing a layer of oxide on the sidewalls of the trenches; and

stripping off the layer of oxide, thereby smoothing the sidewalls and rounding off the bottom portion of the trenches.

17. The method of claim 16, further comprising, before the step of growing the layer of oxide, isotropically dry etching the sidewalls of the trenches, thereby smoothing the sidewalls and rounding off the top and bottom portion of the trenches.

18. The method of claim 13, further comprising forming an additional body region of the second conductivity type in the substrate and extending from the principal surface at a central portion of the source region into the substrate to a depth different than that of the body region.

19. The method of claim 13, wherein the step of forming a masking layer comprises defining a rectangular shaped mask portion at each corner of the cell.

20. The method of claim 13, further comprising the step of determining an area of a portion of the masking layer covering the principal surface at the corner as being dependent on a width of the trenches and process alignment techniques.

21. The method of claim 13, wherein the step of forming the source region includes forming the extent of the source region to be adjacent to one of the trenches at a side of the cell away from the corner of the cell.