ESD protection structure using LDMOS diodes with thick copper interconnect

• US 5,468,984 A
• Filed: 11/02/1994
• Issued: 11/21/1995
• Est. Priority Date: 11/02/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Efland, Taylor R., Skelton, Dale J., Cotton, Dave
• Primary Examiner(s): LARKINS, WILLIAM
• Application Number:
  US08/333,407
• Time in Patent Office: 384 Days
• Field of Search: 257/356, 257/328, 257/762, 437/49, 437/195
• US Class Current: 257/356
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/983 Zener diodes

Abstract

An interconnection structure and method for a multiple zener diode ESD protectoin circuit for power semiconductor devices. A plurality of lateral Zener diodes is formed. Each device is formed of a plurality of cathode and anode diffusion regions to be coupled together to form the cathode and anode of one or more Zener diodes. Each diffusion region has a first metal layer stripe formed over it and in electrical contact with it. A second metal layer conductor is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a bus. A thick third metal layer is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive material, such as copper. The resulting Zener diodes are coupled together in an ESD structure using the second level busses and the thick copper third level busses. The ESD structure of the preferred embodiment has low overall resistance and fast time to breakdown and provides excellent protection for the circuits to be protected. Other devices, systems and methods are also disclosed.

Claims

1. An ESD protection circuit for LDMOS devices, comprising:

a gate input for coupling to the gate terminal of an LDMOS transistor;

a reference voltage input for coupling to a reference voltage; and

a plurality of zener diodes serially coupled between said gate input and said reference voltage input, each one of said zener diodes comprising;

a diffusion well diffused into a semiconductor substrate;

a plurality of cathode diffusion regions of a first semiconductivity type;

a plurality of anode diffusion regions of a second semiconductivity type, spaced apart from an interdigitated with said cathode diffusions so that said anode and cathode diffusions alternate;

a plurality of first metal cathode stripes, each overlying and in electrical contact with a respective one of said cathode diffusions;

a plurality of first metal anode stripes, each overlying and in electrical contact with a respective one of said anode diffusions;

a second metal anode buss partially overlying each of said first metal anode stripes and each of said first metal cathode stripes, and selectively electrically contacting said first metal anode stripes;

a second metal cathode buss spaced apart from said second metal anode buss, said second metal cathode buss partially overlying each of said first metal anode stripes and each of said first metal cathode stripes, and selectively electrically contacting said first metal cathode stripes;

a thick copper third level anode shorting buss partially overlying and in electrical contact with said second metal anode buss, said thick copper third level anode shorting buss substantially lowering the resistance of the diode anode; and

a thick copper third level cathode shorting buss partially overlying and in electrical contact with said second metal cathode buss, said thick copper third level cathode shorting buss substantially lowering the resistance of the diode cathode.

2. A method for providing a ESD protection for an LDMOS transistor, comprising the steps of:

providing a gate input coupled to the gate terminal for the LDMOS transistor;

providing a voltage reference input coupled to a reference voltage; and

providing a plurality of zener diodes serially coupled between said gate input and said reference voltage by performing the steps of;

providing a diffusion well diffused into a semiconductor substrate;

providing a plurality of cathode diffusions diffused into said diffusion well;

providing a plurality of anode diffusions diffused into said diffusion well, said anode and cathode diffusions being spaced apart and alternating;

providing a plurality of first metal anode stripes, each one overlying and in electrical contact with a respective one of said anode diffusions;

providing a plurality of first metal cathode stripes, each one overlying and in electrical contact with a respective one of said cathode diffusions;

providing a second metal anode buss partially overlying each of said first metal anode stripes and said first metal cathode stripes, said second metal anode buss electrically contacting said first metal anode stripes;

providing a second metal cathode buss partially overlying each of said first metal cathode stripes and said first metal anode stripes, said second metal cathode buss electrically contacting said first metal cathode stripes;

providing a copper third level anode shorting buss partially overlying and electrically contacting said second metal anode buss, said thick copper third level anode shorting buss substantially lowering the resistance of said diode anode; and

providing a copper third level cathode shorting buss partially overlying and electrically contacting said second metal cathode buss, said copper third level cathode shorting buss substantially lowering the resistance of said diode cathode.