Semiconductor device and method for forming the same

• US 5,468,987 A
• Filed: 03/25/1993
• Issued: 11/21/1995
• Est. Priority Date: 03/06/1991
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takamura, Yasuhiko, Yamazaki, Shunpei, Zhang, Hongyong
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): Abraham, Fetsum
• Application Number:
  US08/037,162
• Time in Patent Office: 971 Days
• Field of Search: 257/309, 257/388, 257/347, 257/324, 257/406, 257/411, 257/412, 257/640
• US Class Current: 257/412
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate eiectrode and the gate insulating film to prevent invasion of movable ions into a channel, and also to prevent the breakdown of the gate insulating film due to a potential difference between the gate electrode and the channel region. By coating a specific portion of the gate eiectrode with metal material such as chrome or the like for the anodic oxidation, and then removing only the metal material such as chrome or the like together with the anodic oxide of the metal material such as chrome or the like, an exposed portion of metal gate (e.g. aluminum) is formed, and an upper wiring is connected to the exposed portion. Further, an aluminum oxide or silicon nitride is formed as an etching stopper between the gate electrode and the gate insulating film or between the substrate and the layer on the substrate, so that the over-etching can be prevented and the flatness of the eiement can be improved. In addition, a contact is formed in no consideration of the concept "contact hole".

Claims

1. An insulated gate thin film transistor comprising:

a semiconductor layer formed on an insulating surface having source, drain and channel regions therein;

a first insulating layer provided on said semiconductor layer;

a second insulating layer located over said channel region with said first insulating layer therebetween, said second insulating layer having opposed side edges;

a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween; and

an anodic oxide coating covering a surface of said gate electrode, said oxide coating being formed by anodic oxidizing a surface of said gate electrode,

wherein said first insulating layer extends beyond said side edges of the second insulating layer to cover a major surface of said source and drain regions and said side edges of the second insulating layer are approximately coextensive with edges of said anodic oxide coating.

2. The transistor of claim 1 wherein said side edges of said second insulating layer approximately correspond to boundaries between said source and channel regions and between said drain and channel regions.

3. An insulated gate field effect transistor comprising:

a semiconductor layer formed on an insulating surface having source, drain and channel regions therein;

a first insulating layer provided on said semiconductor layer;

a second insulating layer laminated on said first insulating layer;

a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween; and

an anodic oxide coating formed on said gate electrode,

wherein a boundary between said source and channel regions and a boundary between said drain and channel regions are each approximately aligned with side edges of both said first insulating layer and said second insulating layer.

4. The transistor of claim 3 wherein said side edges of both said first insulating layer and said second insulating layer are substantially aligned with side edges of said anodic oxide coating.

5. An insulated gate thin film transistor comprising:

a semiconductor layer formed on an insulating surface having source, drain and channel regions therein;

a first insulating layer provided on said semiconductor layer;

a second insulating layer located over said channel region with said first insulating layer therebetween, said second insulating layer having opposed side edges;

a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween,

wherein said first insulating layer extends beyond said side edges of the second insulating layer to cover a major upper surface of said source and drain regions.

6. The transistor of claim 5 Wherein said side edges of said second insulating layer approximately correspond to boundaries between said source and channel regions and between said drain and channel regions, respectively.

7. The transistor of claim 5 wherein said first insulating layer is provided with at least one contact hole on one of said source and drain regions.

10. The insulated gate thin film transistor of claim 5 or 8 wherein said first insulating layer comprises a different material from said second insulating material.

11. The transistor of claim 5 or 8 wherein said first insulating layer and said second insulating layer each comprises a material selected from the group consisting of aluminum oxide, silicon nitride, silicon oxide and phosphosilicate glass.

12. The transistor of claim 5 or 8 wherein said first insulating layer comprises silicon oxide while said second insulating layer comprises altoninure oxide or silicon oxide.

13. The transistor of claim 5 or 8 wherein said second insulating layer has a higher conductivity than said first insulating layer.

14. The transistor of claim 5 or 8 wherein said gate electrode is covered with an oxide coating formed by anodic oxidizing a surface of said gate electrode.

8. An insulated gate field effect transistor comprising:

a semiconductor layer formed on an insulating surface having source, drain and channel regions therein;

a first insulating layer provided on said semiconductor layer;

a second insulating layer located over said channel region with said first insulating layer therebetween;

a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween,

wherein both of said first insulating layer and said second insulating layer cover an upper surface of said source, drain and channel regions.

9. The transistor of claim 8 wherein at least one contact hole is provided for one of said source and drain regions through said first and second insulating layer.

15. An insulated gate thin film transistor comprising:

a semiconductor layer having source, drain and channel regions therein;

a first insulating layer contacting said semiconductor layer;

a second insulating layer laminated on said first insulating layer;

a gate electrode provided adjacent to said channel region with said first insulating layer and said second insulating layer interposed therebetween; and

an anodic oxide coating formed on said gate electrode,

wherein said second insulating layer has a higher conductivity than said first insulating layer.

16. The transistor of claim 15 wherein said first insulating layer comprises silicon oxide.

17. The transistor of claim 16 wherein said second insulating layer comprises a silicon nitride where the proportion of nitrogen with respect to silicon is 1 to 4/3.