Static current testing apparatus and method for current steering logic (CSL)

• US 5,469,076 A
• Filed: 10/20/1993
• Issued: 11/21/1995
• Est. Priority Date: 10/20/1993
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: HP Inc.
• Inventors: Linn, Scott, Badyal, Rajeev
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/140,348
• Time in Patent Office: 762 Days
• Field of Search: 307/455, 307/296.1, 307/296.6, 307/296.8, 324/522, 324/527, 371/22.1, 371/22.6, 326/16, 326/115, 327/541, 327/543
• US Class Current: 326/16
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence

Abstract

A static current testing method for single-ended or differential logic circuits having a static bias current in normal operation. The static current testing method includes switching a first bias node between a first bias voltage, in a normal operational mode, and a first shut-off voltage, in a first static current testing phase, and measuring the current supplied to the logic circuit in the testing phase. For differential circuits, the static current testing method further includes an additional step of switching a second bias node between the second bias voltage in the normal operational mode and the second shut-off voltage in a second static current testing phase. A bias switching means is used to switch between the normal bias voltage and the testing voltage. A cell switching means is coupled to a diode-connected transistor for forcing the circuit output low and for isolating the diode-connected transistor from the output.

Claims

1. A logic circuit comprising:

a folded source coupled logic gate having an input, an output, and a bias node, the logic gate consuming a substantially constant current during a normal operating mode; and

bias switching means for switching the bias node between a source of bias voltage in the normal operating mode and a source of shut-off voltage in a static current testing mode.

2. A logic circuit according to claim 1 in which the bias switching means comprises a multiplexer having a first input for receiving the bias voltage, a second input for receiving the shut-off voltage, an output coupled to the bias node, and a control input for receiving a select signal for selecting between the bias voltage and the shut-off voltage.

3. A logic circuit comprising:

a static current logic gate having an input, an output, and a bias node, the static current logic gate including a diode-connected transistor having a gate and a drain forming an anode coupled to the output; and

bias switching means for switching the bias node between a source of bias voltage in a normal operating mode and a source of shut-off voltage in a static current testing mode.

4. A logic circuit according to claim 3 in which the static current logic gate further comprises means for isolating the diode-connected transistor from the output in the static current testing mode.

5. A logic circuit according to claim 4 in which the isolating means includes

a first transistor interposed between the drain and the gate of the diode-connected transistor and having a gate for receiving a first select signal.

21. A logic circuit according to claim 4 in which the static current logic gate further comprises means for forcing the output to a logic low level in the static current testing mode.

22. A logic circuit according to claim 21 in which the forcing means includes a second transistor having a first node coupled to the output, a second node coupled to ground, and a gate for receiving a second select signal.

6. A differential logic circuit comprising:

a static current logic gate having first and second differential inputs, first and second differential outputs, and first and second bias nodes;

first bias switching means for switching the first bias node between a first source of bias voltage in a normal operating mode and a first source of shut-off voltage in a first static current testing phase; and

second bias switching means for switching the second bias node between a second source of bias voltage in the normal operating mode and a second source of shut-off voltage in a second static current testing phase.

7. A logic circuit according to claim 6 in which the first bias switching means comprises a first multiplexer having a first input for receiving the first bias voltage, a second input for receiving the first shut-off voltage, an output coupled to the first bias node, and a first control input for receiving a first select signal for selecting between the first bias voltage and the first shut-off voltage.

8. A logic circuit according to claim 6 in which the second bias switching means comprises a second multiplexer having a first input for receiving the second bias voltage, a second input for receiving the second shut-off voltage, an output coupled to the second bias node, and a second control input for receiving a second select signal for selecting between the second bias voltage and the second shut-off voltage.

9. A logic circuit according to claim 6 in which the static current logic gate includes:

a first diode-connected transistor having a gate and a drain forming an anode coupled to the first differential output; and

a second diode-connected transistor having a gate and a drain forming an anode coupled to the second differential output.

10. A logic circuit according to claim 9 in which the static current logic gate further comprises:

first means for forcing the first differential output to a predetermined logic level in the second static current testing phase;

first means for isolating the first diode-connected transistor from the first differential output in the second static current testing phase;

second means for forcing the second differential output to the predetermined logic level in the second static current testing phase; and

second means for isolating the diode-connected transistor from the output in the second static current testing phase.

11. A logic circuit according to claim 10 in which the first forcing means includes

a first transistor interposed between the drain and the gate of the first diode-connected transistor and having a gate for receiving a first select signal;

and in which the first isolating means includes

a second transistor having a first node coupled to the output, a second node coupled to ground, and a gate for receiving a second select signal.

12. A logic circuit according to claim 10 in which the second forcing means includes

a first transistor interposed between the drain and the gate of the second diode-connected transistor and having a gate for receiving a first select signal;

and in which the second isolating means includes

a second transistor having a first current node coupled to the output, a second current node coupled to ground, and a gate for receiving a second select signal.

13. A static current testing method for logic circuits comprising:

providing a logic circuit including a static current logic gate having an input, a bias node for receiving a bias voltage, and an output;

switching the bias node between a source of bias voltage in a normal operational mode and a source of shut-off voltage in a static current testing mode; and

measuring a static current consumed by the logic gate

14. A static current testing method according to claim 13 further comprising the step of comparing the measured static current to a predetermined failure limit.

15. A static current testing method according to claim 13 further comprising the step of detecting when the measured current is greater than a predetermined failure limit.

16. A static current testing method according to claim 13 further comprising:

switching the bias node from the source of shut-off voltage to the source of bias voltage;

forcing the inputs and outputs of the logic gate to a logic low level during a second phase of the static current testing mode;

measuring a static current consumed by the logic gate during the second phase of the static current testing mode.

17. A static current testing method according to claim 16 further comprising the step of comparing the measured static current to a predetermined failure limit.

18. A static current testing method for logic circuits comprising:

providing a logic circuit including a static current logic gate having a pair of differential inputs, a first bias node for receiving a first bias voltage, a second bias node for receiving a second bias voltage, and a pair of differential outputs;

applying the first bias voltage to the first bias node during a normal mode;

applying the second bias voltage to the second bias node during the normal mode;

switching the first bias node between the first bias voltage and a first shut-off voltage in a first static current testing phase; and

measuring a static current consumed by the logic gate in the first testing phase.

19. A static current testing method according to claim 18 further comprising the step of switching the second bias node between the second bias voltage in the normal mode and a second shut-off voltage in a second static current testing phase.

20. A static current testing method according to claim 19 further comprising the step of detecting when the measured current is greater than a predetermined failure limit.

23. A static current testing method according to claim 18 further comprising the step of forcing the differential inputs and the differential outputs of the logic gate to a logic low level during the second static current testing phase.