Data slice circuit

• US 5,469,091 A
• Filed: 11/20/1992
• Issued: 11/21/1995
• Est. Priority Date: 03/25/1991
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Takahashi, Shinichi, Yagi, Yukihiro, Nakaimuki, Masayuki
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): TRAN, TOAN V
• Application Number:
  US07/952,724
• Time in Patent Office: 1,096 Days
• Field of Search: 307/354, 307/350, 307/359, 307/261, 328/28, 328/31, 328/32, 327/72, 327/73, 327/63, 327/77, 327/78, 327/79, 327/87, 327/89, 327/100, 327/113, 327/114, 327/172, 327/173, 327/174, 327/175, 327/184
• US Class Current: 327/73
• CPC Class Codes: H04L 25/063 Setting decision thresholds using feedback techniques only
• CPC Class Codes: H04N 7/0355 for discrimination of the binary level of the digital data, e.g. amplitude slicers

Abstract

A data slice circuit is provided for slicing the caption data or the likes included in a television signal at an optimum voltage. A product between a clock-run signal sliced by a comparator at a tentative reference voltage and a clock signal which is 16 times the clock-run signal is stored in a shift register as 16 bit information, and out of them, only the 8 bits around its center are taken in a duty-factor check block, thereby judging the suitability of the slice level. Based on the result obtained, the value of the counter is increased or decreased, and it is taken as a renewed reference voltage through a pulse width conversion circuit and an integration circuit. Also with data sliced by a renewed reference voltage, the check is executed similarly, and a slicing action at an optimum level is achieved.

Claims

1. A data slice circuit comprising:

comparison means for issuing a result of comparison of an arbitrary one period of a data signal with a first reference voltage;

product means for producing a product of an output of said comparison means and a signal having a frequency of at least two times a frequency of said data signal;

bit storage means for storing an output of said product means as a bit train;

duty-factor check means for checking a duty-factor of said data signal of said arbitrary one period by checking said bit train stored in said bit storage means in compliance with a predetermined rule; and

reference voltage variation means for varying said first reference voltage in accordance with an output of said duty-factor check means and for providing said first reference voltage to said comparison means.

2. A data slice circuit comprising:

reference voltage generating means for generating a reference voltage;

comparison means for comparing said reference voltage with a data signal having a first frequency;

sampling means for sampling an output of said comparison means at a second frequency, said second frequency being greater than "n" times said first frequency, "n" being greater than two;

sampling start means for starting said sampling means when said output of said comparison means changes;

memory means for storing a result of said sampling means as a series of binary data;

duty-factor check means for detecting a duty factor of said data signal on a basis of said series of binary data;

a counter for counting at said second frequency when said output of said comparison means changes, and for outputting an overflow signal when a count value of said counter becomes equal to "n", said overflow signal signalling said duty-factor check means to detect said duty factor;

sampling stop means for stopping said sampling means according to said overflow signal; and

reference voltage variation means for increasing said reference voltage in a first case that said binary data corresponding to an amount that said data signal is higher than said reference voltage is more than a predetermined upper limit value, and for decreasing said reference voltage in a second case that said binary data corresponding to an amount that said data signal is lower than said reference voltage is less than a predetermined lower limit value in said series of binary data, according to said duty factor.

4. A data slice circuit in accordance with claim 2, characterized in that said reference voltage is not changed when all of said series of binary data are data representing that said data signal is lower than said reference voltage.

3. A data slice circuit comprising:

reference voltage generating means for generating a reference voltage;

comparison means for comparing said reference voltage and a data signal having a first frequency;

sampling means for sampling an output of said comparison means at a rate having a second frequency of "m", "m" being greater than four times said first frequency;

sampling start means for starting said sampling means when said output of said comparison means changes;

memory means for storing a result of said sampling means as a series of binary data;

a counter for counting an output of said sampling means when said output of said comparison means changes, and for outputting an overflow signal when a count value of said counter becomes equal to "m";

sampling stop means for stopping said sampling means according to said overflow signal; and

reference voltage variation means for increasing said reference voltage in a first case that said binary data corresponding to an amount that said data signal is higher than said reference voltage is more than a predetermined upper limit value, and for decreasing said reference voltage in a second case that said binary data corresponding to an amount that said data signal is lower than said reference voltage is less than a predetermined lower limit value in said series of binary data, according to data extracted from a part of said stored binary data which is included in a substantially same time period before and after a center of one sampling period of said sampling means in said series of binary data stored in said memory means.

5. A data slice circuit in accordance with claim 3, characterized in that said reference voltage is not changed when all of said series of binary data are data representing that said data signal is lower than said reference voltage.