Charge pumping circuit using non-overlapping clock control

• US 5,469,110 A
• Filed: 06/27/1994
• Issued: 11/21/1995
• Est. Priority Date: 06/27/1994
• Status: Expired due to Fees

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Liao, Tsuoe-Hsiang
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Zwiezig, Jeffrey
• Application Number:
  US08/265,748
• Time in Patent Office: 512 Days
• Field of Search: 257/299, 307/109, 307/110, 327/156, 327/157, 327/239, 327/259, 327/306, 327/333, 327/390, 327/535, 327/536, 327/537, 327/589
• US Class Current: 327/536
• CPC Class Codes: G05F 3/24 wherein the transistors are of the field-effect type only G05F3/205, G05F3/26, G05F3/30 take precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A charge pumping circuit generates a negative voltage equal in magnitude to the positive supply voltage. A non-overlapping clock is used to set the voltage across a first capacitor equal to the positive supply voltage through a MOS switch. This stored voltage is then transferred to a second capacitor through a second MOS switch to generate a negative voltage at one terminal of the second MOS switch. The use of MOS switches eliminates the threshold voltage drop if MOS diodes were used to charge the first capacitor or to transfer the voltage from the first capacitor to the second capacitor.

Claims

1. A charge pumping circuit for deriving a negative voltage equal in magnitude to a high-level positive supply voltage, comprising:

oscillator means for generating osicllatory clock signals having a first phase and a second phase in a clock period;

a non-overlapping clock control unit having a first and a second output terminals, said control unit generating two non-overlapping out-of-phase clock signals at said first and said second output terminals respectively in response to said oscillatory clock signals;

a first capacitor;

a charging and discharging means, controlled by said non-overlapping clock signals from said oscillator means, for charging said first capacitor to a voltage value equal to said high-level positive supply voltage during said first phase and discharging said first capacitor during said second phase;

a second capacitor having a negative voltage output terminal;

transferring means, controlled by said non-overlapping clock signals from said second output terminal, for maintaining a voltage value output at said negative voltage terminal during said first phase and transferring charges discharged from said first capacitor to said second capacitor during said second phase so that after a plurality of said oscillatory clock periods, said negative voltage is derived at said negative voltage output terminal of said second capacitor;

said charging and discharging means comprising delay means connected between said oscillator means and said first capacitor.

2. A charge pumping circuit as described in claim 1, further comprising :

a first switch connected between said first capacitor and ground potential and controlled by said non-overlapping clock signals from said first output terminal of said non-overlapping clock control unit; and

a first level shifting circuit connected between said first output terminal of said non-overlapping clock control unit and said first capacitor for shifting voltage levels of said non-overlapping clock signals from said output terminal of said non-overlapping clock control unit.

3. A charge pumping circuit as described in claim 1, wherein said delay means includes a series of inverters.

4. A charge pumping circuit as described in claim 1, wherein said transferring means comprises:

a second switch connected between said first capacitor and said second capacitor and controlled by said non-overlapping clock signals from said second output terminal of said non-overlapping clock control unit, and

a second level shifting circuit connected between said second output terminal of said non-overlapping clock control unit and said second capacitor for shifting voltage levels of said non-overlapping clock signals from said second output terminal of said non-overlapping clock control unit.

5. A charge pumping circuit, as described in claim 1, wherein said non-overlapping control clock is generated by cross-coupling two logic gates cascaded with inverters and driven from an oscillating signal.