Circuit for generating a process variation insensitive reference bias current

• US 5,469,111 A
• Filed: 08/24/1994
• Issued: 11/21/1995
• Est. Priority Date: 08/24/1994
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Chiu, Kwok-F
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US08/295,331
• Time in Patent Office: 454 Days
• Field of Search: 327/538, 327/540, 327/541, 327/542, 327/543, 327/545, 327/546
• US Class Current: 327/538
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence

Abstract

In a comparator circuit, a reference bias current generation circuit uses an MOS transistor rather than a resistor to generate a current based on the difference between the base-emitter voltages of two bipolar transistors. In one embodiment, a second MOS transistor matched to the first MOS transistor is used to provide a current substantially independent of variations of the threshold voltage due to variations in the manufacturing process. A reference voltage source is provided to adjust the temperature coefficient of the reference bias current.

Claims

1. A reference bias current generation circuit, comprising:

a first bipolar transistor having a collector coupled to a first supply voltage, a base terminal and an emitter terminal;

a second bipolar transistor having a collector coupled to said first supply voltage, a base terminal coupled to said base terminal of said first bipolar transistor and an emitter terminal;

a first MOS transistor having a drain terminal coupled to said emitter terminal of said first bipolar transistor, a gate terminal and a source terminal;

an operational amplifier having a first input terminal coupled to said emitter terminal of said second bipolar transistor and a second input terminal coupled to said source terminal of said first MOS transistor, said operational amplifier providing an output signal having a magnitude indicative of the difference between the voltages at said first and second input terminals;

a first current source coupled between said source terminal of said first MOS transistor and a second supply voltage, said first current source receiving and responsive to said output signal of said operational amplifier;

a second current source coupled to said emitter terminal of said second bipolar transistor and said second supply voltage; and

means, coupled to the base terminal of the first bipolar transistor and the gate terminal of the first MOS transistor, for compensating the current through said first MOS transistor variations due to a shift in the threshold voltage of said first MOS transistor.

2. A reference bias current generation circuit as in claim 1, wherein said means for compensating comprises:

a second MOS transistor having a drain terminal and a gate terminal coupled to said first supply voltage, and a source terminal coupled to said base terminal of said first bipolar transistor;

a third bipolar transistor having a collector terminal and a base terminal coupled to said first supply voltage and an emitter terminal coupled to said gate terminal of said first MOS transistor;

a third current source coupled to said base terminal of said first bipolar transistor and said second supply voltage; and

a fourth current source coupled to said emitter terminal of said third bipolar transistor and said second supply voltage.

3. A reference bias current generation circuit as in claim 2, wherein said gate terminal of said first MOS transistor is coupled to said emitter terminal of said third bipolar transistor via a reference voltage source.

4. A reference bias current generation circuit as in claim 2, wherein said source terminal of said second MOS transistor is coupled to said base terminal of said first bipolar transistor via a reference voltage source.

5. A reference bias current generation circuit as in claim 2, wherein said third current source having a quiescent current which is twice the magnitude of the corresponding current in said first current source.

6. A reference bias current generation circuit as in claim 2, wherein said first and second MOS transistors have the same physical dimensions.