Hybrid integrated circuit device

• US 5,469,131 A
• Filed: 08/30/1993
• Issued: 11/21/1995
• Est. Priority Date: 08/28/1992
• Status: Expired due to Fees

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Takahashi, Ryoichi, Igarashi, Yusuke, Okawa, Katsumi
• Primary Examiner(s): Lateef, Marvin M.
• Application Number:
  US08/114,329
• Time in Patent Office: 813 Days
• Field of Search: 338/306, 338/307, 338/308, 338/309, 338/322, 338/323, 338/325, 338/330, 338/314, 338/331, 338/333, 338/195
• US Class Current: 338/306
• CPC Class Codes: H01C 7/00 Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material consisting of loose powdered or granular material H01C8/00; resistors having potential barriers, e.g. field-effect resistors, H01L29/00; semiconductor devices sensitive to electromagnetic or corpuscular radiation, e.g. photoresistors, H01L31/00; magnetic field controlled resistors H10N50/10; bulk negative resistance effect devices H10N80/00
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/647 Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/12035 Zener diode
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/2075 larger or equal to 1 micron less than 10 microns
• CPC Class Codes: H01L 2924/20754 : larger or equal to 40 microns less than 50 microns
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns
• CPC Class Codes: H01L 2924/20756 : larger or equal to 60 microns less than 70 microns
• CPC Class Codes: H01L 2924/2076 : equal to or larger than 100 microns
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H05K 1/0234 : Resistors or by disposing resistive or lossy substances in or near power planes H05K1/0246 takes precedence
• CPC Class Codes: H05K 1/056 : the metal substrate being covered by an organic insulating layer
• CPC Class Codes: H05K 2201/10477 : Inverted
• CPC Class Codes: H05K 2203/049 : Wire bonding
• CPC Class Codes: H05K 3/328 : by welding

Abstract

A resistive body of a hybrid integrated circuit has a resistance pattern on a resin film. Bonding pads permit connection of current through the resistance pattern. The resistance pattern may form part of a detecting bridge for overcurrent detection. One embodiment of the invention uses a rectangular resistance pattern with an opening in the center to force current to flow on a perimeter path for minimizing maximum temperature. Another embodiment uses a serpentine resistance pattern. A face-down resistance patter reduces interference. A direct-connection bonding pad reduces the voltage generated in a parasitic capacitance to improve the resistance of the resin film to voltage breakdown.

Claims

1. A hybrid integrated circuit device comprising:

a metal substrate;

an insulating resin layer on said metal substrate;

a plurality of conductive paths and a plurality of bottom pads on said insulating resin layer;

said plurality of conductive paths providing connections to a plurality of semiconductor elements affixed to said bottom pads;

means for detecting a current flowing in said semiconductor elements;

said means for detecting including a resistance pattern on a resin film;

said resin film being affixed to said bottom pads;

said resistance pattern having at least a first pair of bonding pads for detecting current and at least a second pair of bonding pads for detecting voltage; and

means for connecting at least one of said at least a first and second pairs to said plurality of conductive paths.

2. A hybrid integrated circuit device as in claim 1, wherein:

said means for connecting includes an aluminum wire having a diameter of about 200 to 400 μ

m connecting to said at least a first pair of bonding pads and an aluminum wire having a diameter of about 40 to 60 mμ

for connecting to said at least a second pair of bonding pads.

3. A hybrid integrated circuit device as in claim 1, wherein said resistance pattern is made of an alloy material which has a temperature coefficient of resistance of from about 1 ppm to about 500 ppm in dimensionless units.

4. A hybrid integrated circuit device as recited in claim 3, wherein said alloy material is composed of 50%-80% by weight of copper and 12%-30% by weight of manganese.

5. A hybrid integrated circuit device as recited in claim 3, wherein said alloy material is composed of 50%-80% by weight of copper and 2%-16% by weight of nickel.

6. A hybrid integrated circuit device as in claim 1, wherein:

said at least a first pair of bonding pads is on one side of said resistance pattern and said at least a second pair of bonding pads for voltage detection is on another side of said resistance pattern;

said means for connecting connects each of said bonding pads to each of said conductive paths;

said means for connecting is a wire; and

said resistance pattern provides a dual path for current flow.

7. A hybrid integrated circuit device comprising:

a metal substrate;

an insulating resin layer on said metal substrate;

a plurality of conductive paths and a plurality of bottom pads on said insulating resin layer;

a resistor for detecting a current flowing in an external element;

said resistor including a resin film;

said resin film being affixed to said bottom pads;

a resistance pattern on said resin film;

said resistance pattern having on one side of said resistance pattern a first pair of bonding pads for detecting current and on another side of said resistance pattern a second pair of bonding pads for detecting voltage; and

means for connecting said first pair of bonding pads to said conductive paths on said one side of said resistance pattern and for connecting said second pair of bonding pads to said conductive paths on said another side of said resistance pattern.

8. A hybrid integrated circuit device comprising:

a metal substrate;

an insulating resin layer on said metal substrate;

a plurality of conductive paths and a plurality of bottom pads on said insulating resin layer;

said plurality of conductive paths providing connections to an external element;

means for detecting a current flowing in said external element;

a resistor having a resin film;

said resin film being affixed to said bottom pads;

a resistance pattern on said resin film;

said resistance pattern having on one side of said resistance pattern a first pair of bonding pads for detecting current and on another side of said resistance pattern a second pair of bonding pads for detecting voltage; and

means for connecting said first pair of bonding pads to said conductive paths on said one side of said resistance pattern and for connecting said second pair of bonding pads to said conductive paths on said another side of said resistance pattern.

9. A hybrid integrated circuit device as recited in claim 8, wherein said resistive means further comprises:

a bottom pad of said resistance pattern;

said bottom pad being mounted directly on said conductive path corresponding to said first pair of bonding pads;

said means for connecting being a solder connection.

10. A hybrid integrated circuit device comprising:

a metal substrate;

an insulating resin layer on said metal substrate;

a plurality of conductive paths and a plurality of bottom pads on said insulating resin layer;

said plurality of conductive paths providing connections to an external element;

means for detecting a current flowing in said external element;

said means for detecting including a resin film;

said resin film being affixed to said bottom pads;

a resistance pattern on said resin film;

said resistance pattern having on one side of said resistance pattern a pair of bonding pads for detecting current and on another side of said resistance pattern at least first, second and third bonding pads for detecting voltage;

means for connecting said pair of bonding pads to said conductive paths; and

means for connecting a selectable two of said at least first, second and third bonding pads to said conductive paths, whereby a selectable voltage signal is determined by said selectable two.

11. A hybrid integrated circuit device comprising:

a metal substrate;

an insulating resin layer on said metal substrate;

a plurality of conductive paths and a plurality of bottom pads on said insulating resin layer;

said plurality of conductive paths providing connections to external elements;

means for detecting a current flowing in said external elements;

said means for detecting including a resin film;

said resin film being affixed to said bottom pads;

a resistance pattern on said resin film;

said resistance pattern having on one side of said resistance pattern a first pair of bonding pads for detecting current and on another side of said resistance pattern a second pair of bonding pads for detecting current; and

said resistance pattern having the foregoing components being, in a facedown condition, disposed on said plurality of conductive paths so that said first pair of bonding pads and said second pair of bonding pads can connect directly to said plurality of conductive paths; and

means for connecting said first and second pairs of bonding pads directly to said plurality of conductive paths.

12. A hybrid integrated circuit device as recited in claim 11, wherein:

said resistive means includes an electrically insulating resin between said resistance pattern and said substrate; and

said electrically insulating resin being of a type providing substantial thermal conductivity, whereby heat generated in said resistance pattern is conducted to said substrate.

13. A hybrid integrated circuit device as recited in claim 12, wherein said insulating resin is an epoxy resin composed of about 57% by weight of an inorganic filler having a good thermal conductivity.

14. A resistance element for a hybrid integrated circuit comprising:

a resin film;

a resistance pattern on said resin film;

at least a first and second spaced-apart bonding pads on said resistance pattern for connecting a current through said resistance pattern;

means for distributing a current flow over said resistance pattern including an opening in a central region of said resistance pattern effective to force current to flow about a perimeter of said resistance pattern; and

means for connecting current to said at least a first and second spaced-apart bonding pads, wherein said means for connecting includes means for minimizing magnetic interference with an output of said resistance pattern.

15. A resistance element according to claim 14, further comprising means for distributing a current flow over said resistance pattern.

16. A resistance element according to claim 15, wherein:

said resistance pattern is generally rectangular.

17. A resistance element according to claim 14, wherein said means for minimizing magnetic interference includes means for connecting a voltage signal for flow in a first direction and means for connecting a current signal for flow in a second direction.

18. A resistance element according to claim 14, wherein:

said resistance pattern is a serpentine pattern; and

said at least first and second spaced-apart bonding pads includes first and second pairs of bonding pads;

said first pair of bonding pads being disposed at ends of said serpentine pattern, on a first side thereof; and

said second pair of bonding pads being disposed at intermediate positions on said serpentine pattern, on a second side thereof.