AC timing asymmetry reduction circuit including summing DC offset voltage with timing signal

• US 5,469,305 A
• Filed: 12/17/1993
• Issued: 11/21/1995
• Est. Priority Date: 12/17/1993
• Status: Expired due to Term

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology plc (Seagate Technology Holdings Plc)
• Inventors: Machelski, Russell J., Madsen, Timothy A.
• Primary Examiner(s): Psitos, Aristotelis
• Assistant Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US08/169,423
• Time in Patent Office: 704 Days
• Field of Search: 360/51, 360/45, 360/46, 360/66, 360/67, 360/68, 360/61, 375/76, 375/110, 307/491, 307/296.6, 307/354, 307/527, 307/491, 328/123, 328/162, 455/214, 371/6, 371/48, 327/362
• US Class Current: 360/51
• CPC Class Codes: G11B 5/035 Equalising
• CPC Class Codes: G11B 5/09 Digital recording
• CPC Class Codes: H03F 3/45977 using switching means, e.g. sample and hold

Abstract

A DC offset voltage is added to the analog timing signal in a peak detection data recovery circuit to cancel the timing asymmetry from a magnetoresistive head signal. An AC timing asymmetry cancellation circuit uses a charge pump, buffer amplifier and resistor divider to produce the proper DC offset voltage automatically.

Claims

1. In a data recovery system which reads data from a magnetic medium and which derives timing information from a comparator, a method to compensate for AC timing asymmetry comprising:

detecting data transitions in the form of timing signals;

iteratively accumulating an approximate DC offset voltage based on timing asymmetry in the timing signal, the approximate DC offset voltage of successive iterations converging on an accurate offset voltage;

dividing the approximate DC offset voltage;

controlling the DC offset voltage division by predetermined switching of the approximate DC offset voltage between an active and an inactive state; and

summing the divided DC offset voltage and the timing signal.

2. The method of claim 1 wherein the DC offset is generated using charge pump cycles derived from a timing signal and an encoder clock signal.

3. The method of claim 2 wherein the DC offset voltage generated by a timing asymmetry cancellation circuit results in cancellation of timing asymmetry in a 4T timing signal.

4. The method of claim 2 wherein the DC offset voltage generated by the timing asymmetry in a 3T timing signal.

5. The method of claim 2 wherein the DC offset voltage division is inactive during the charge pump cycles and is active during reading of user data.

6. In a data recovery system which reads data from a medium and which derives timing information from the medium, an apparatus for compensating for AC timing asymmetry, comprising:

means for generating a timing signal based on timing of data read from the magnetic medium;

DC offset voltage generator means for iteratively generating and accumulating an approximate DC offset voltage based on timing asymmetry contained in a timing signal, the approximate DC offset voltage of successive iterations converging on an accurate offset voltage;

dividing means for dividing the approximate DC offset voltage to obtain a divided DC Offset voltage;

switching means for controlling the dividing means by predetermined switching of the approximate DC offset voltage between an active and an inactive state; and

summing means for summing the divided DC offset voltage and the timing signal.

7. The data recovery system of claim 6 wherein the DC offset generator means comprises a charge pump circuit.

8. In a data recovery system which reads data from a magnetic medium and which derives timing information from a comparator, an apparatus to compensate for AC timing asymmetry comprising:

a charge pump logic circuit to receive a timing signal and to produce a charge pump cycle characterized by a pump up and a pump down signal, the charge pump logic circuit including a read gate to initiate a burst of multiple charge pump cycles;

a capacitor;

a charge pump which acts to charge the capacitor when the pump up signal is active and to drain the capacitor when the pump down signal is active; and

summing means for summing the capacitor charge and the timing signal.

9. The data recovery system of claim 8 wherein a discharge switch is connected to the capacitor.

10. The data recovery system of claim 9 wherein the discharge switch is used to discharge the capacitor during a head selection operation.

11. The data recovery system of claim 9 wherein the discharge switch is used to discharge the capacitor during a seek operation.

12. In a data recovery system which reads data from a magnetic medium and which derives timing information from the medium, an apparatus for compensating for AC timing asymmetry comprising:

means for operating a charge pump logic circuit wherein the circuit is responsive to positive asymmetry in a timing signal to generate a pump up signal and is responsive to negative asymmetry in the timing signal to generate a pump down signal, the charge pump logic circuit including a read gate to initiate a burst of multiple charge pump cycles;

DC offset voltage generator means responsive to the pump up and pump down signals for iteratively, generating and accumulating an approximate DC offset voltage based on based on successive bursts of cycles of pump up and pump down signal; and

means for summing the approximate DC offset voltage and the timing signal.

13. In a data recovery system which reads data from a first sector of a first track of a magnetic disc, a method of compensating for AC timing asymmetry in a data timing signal, the method comprising:

iteratively deriving and accumulating an approximate DC offset-canceling voltage according to an AC timing asymmetry, the approximate DC offset voltage of successive iterations converging on an accurate offset voltage;

summing the approximate DC offset-canceling voltage and the timing signal; and

dividing the approximate offset-canceling voltage after a predetermined number of iterations.

14. The method of claim 13 further comprising resetting the offset-canceling voltage to zero.

15. The method of claim 14 wherein resetting occurs before reading from a second sector of the first track of the magnetic disc.