Row redundancy circuit suitable for high density semiconductor memory devices

• US 5,469,388 A
• Filed: 11/23/1993
• Issued: 11/21/1995
• Est. Priority Date: 11/23/1992
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Chan-Jong
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Hoang, Huan
• Application Number:
  US08/155,747
• Time in Patent Office: 728 Days
• Field of Search: 365/210, 365/225.7, 365/200, 365/201, 365/230.06, 371/10.1, 371/10.2, 371/10.3
• US Class Current: 365/200
• CPC Class Codes: G11C 29/781 combined in a redundant decoder
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme

Abstract

A semiconductor memory device has a plurality of memory cell arrays, each with a normal cell array and a spare cell array. Fuse circuits are programmable to substitute a spare-cell-array word line for a defective word line in any normal cell array. When a defective word line is addressed, a fuse circuit activates a spare-cell-array word line, and also activates a redundancy signal line. A single redundancy signal line is shared by all fuse circuits and block select circuits. Block select circuits normally enable the cell array that includes the defective word line, however, the block select circuits are disabled when the defective word line has been replaced by a spare word line an another block.

Claims

1. A semiconductor memory device comprising:

a plurality of memory cell arrays, each memory cell array including a normal cell array and a spare cell array;

a plurality of decoders for addressing memory cell arrays; and

a row redundancy circuit that is programmable to substitute a row in a spare cell array for a defective row in any normal cell array responsive to a single redundancy enable signal supplied to each of said plurality of memory cell arrays through a single bus line.

2. The memory of claim 1 wherein the row redundancy circuit comprises:

a plurality of fuse circuits, each programmable to substitute a spare word line for a defective word line in any normal cell array; and

a redundancy signal line actuable by any fuse circuit when a spare word line is activated by address signals for a defective word line in said normal cell array.

3. The memory of claim 1 wherein the row redundancy circuit comprises:

a plurality of block select circuits, each enabling an associated cell array when an addressed word line is in the associated cell array, except when a spare word line in another cell array has been substituted for the addressed word line.

4. The memory of claim 1 wherein the row redundancy circuit comprises:

a plurality of fuse circuits, each associated with a memory cell array and programmable to substitute a spare word line for a defective word line in any normal cell array;

a redundancy signal line actuable by any fuse circuit when a spare word line is activated by address signals for a defective word line in a normal cell array; and

a plurality of block select circuits, each associated with a memory cell array and a fuse circuit, each enabling its associated cell array when an addressed word line is in the associated cell array, except when the redundancy signal is activated by a fuse circuit other than its associated fuse circuit.

5. The memory of claim 1 wherein the row redundancy circuit comprises:

a plurality of fuse circuits, each programmable to substitute a spare word line for a defective word line in any normal cell array;

a redundancy signal line actuable by any fuse circuit when a spare word line is activated by address signals for a defective word line in a normal cell array; and

a plurality of block select circuits, each enabling an associated cell array when an addressed word line is in the associated cell array, except when a spare word line in another cell array has been substituted for the addressed word line.

6. The semiconductor memory device of claim 1, wherein said single bus line is arranged in a peripheral circuit.

7. A semiconductor memory device comprising:

a plurality of memory cell arrays, each memory cell array including a normal cell array and a spare cell array;

a plurality of decoders for addressing memory cell arrays;

a plurality of fuse circuits, each programmable to substitute a spare word line for a defective word line in any normal cell array;

a redundancy signal line actuable by any fuse circuit when a spare word line is activated by address signals for a defective word line in a normal cell array; and

a plurality of block select circuits enabled by a redundancy enable signal provided to each of said plurality of memory cell arrays through a single bus line, each block select circuit enabling an associated cell array when an addressed word line is in the associated cell array, except when a spare word line in another cell array has been substituted for the addressed word line.

8. The semiconductor memory device of claim 7, wherein said single bus line is arranged in a peripheral circuit.

9. A semiconductor memory device comprising:

a plurality of memory cell arrays, each memory cell array including a normal cell array and a spare cell array;

a plurality of decoders for addressing memory cell arrays;

a plurality of fuse circuits, each associated with a memory cell array and programmable to substitute a spare word line for a defective word line in any normal cell array;

a redundancy signal line actuable by any fuse circuit when a spare word line is activated by address signals for a defective word line in a normal cell array; and

a plurality of block select circuits, each associated with a memory cell array and a fuse circuit and enabled by a redundancy enable circuit supplied to each of said plurality of memory cell arrays through a single bus line, each block select circuit enabling its associated cell array when an addressed word line is in its associated cell array, except when the redundancy signal is activated by a fuse circuit with which the block select circuit is not associated.

10. The semiconductor memory device of claim 9, wherein said single bus line is arranged in a peripheral circuit.