Distributed frame processing for time division multiplexing
First Claim
1. A time division multiplexer for multiplexing data from a plurality of channels, comprising:
- a) a high speed bus having a first data rate;
b) a means for synchronizing;
c) a system communication manager means coupled to said high speed bus, and including intelligent processing means for generating a data frame;
d) a plurality of processors, each having a memory which stores said data frame, each one of said processors being coupled between a respective one of said channels and said high speed bus, and each of said processors being synchronized by said means for synchronizing, wherein said system communication manager means for transmitting said data frame to said plurality of processors over said high speed bus at predetermined times and at an effective second data rate slower than said first data rate, whereupon each of said processors stores said data frame in its memory, and said system communication manager means for causing said means for synchronizing to generate a synch signal which synchronizes said processors, wherein,said data frame comprises a first sequence of instructions for said plurality of processors coupled to said channels, which instructions instruct said processors as to when to place data on said high speed bus, and each of said plurality of processors synchronously and simultaneously runs said data frame and places data on said high speed bus according to said instructions of said data frame when the channel with which a particular processor is associated is indicated by said data frame.
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Accused Products
Abstract
A time division multiplexer (TDM) is provided for multiplexing data from a plurality of channels. The TDM system generally comprises a high speed time division multiplexed digital data bus, a synchronizing bus, a plurality of channel cards coupled between the data channels and the data bus with each channel card having its own processor and memory, and a system communication manager (SCM) which is also coupled to the digital bus, and includes a (micro)processor. The processor of the SCM determines the frame for the system and initially forwards the frame information to each of the channel cards during predetermined time slots of the high speed data bus. The channel cards are synchronized by the SCM via the synchronization bus, and the channel cards use the synchronization information and the framing information in order to appropriately place data on and take data off of the high speed data bus without the use of an address bus. A system overhead frame (SOF) is also preferably multiplexed into timeslots of the high speed data bus. Thus, during operation, the high speed data bus multiplexes not only data from the channel cards, but system overhead information as well as framing information.
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Citations
20 Claims
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1. A time division multiplexer for multiplexing data from a plurality of channels, comprising:
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a) a high speed bus having a first data rate; b) a means for synchronizing; c) a system communication manager means coupled to said high speed bus, and including intelligent processing means for generating a data frame; d) a plurality of processors, each having a memory which stores said data frame, each one of said processors being coupled between a respective one of said channels and said high speed bus, and each of said processors being synchronized by said means for synchronizing, wherein said system communication manager means for transmitting said data frame to said plurality of processors over said high speed bus at predetermined times and at an effective second data rate slower than said first data rate, whereupon each of said processors stores said data frame in its memory, and said system communication manager means for causing said means for synchronizing to generate a synch signal which synchronizes said processors, wherein, said data frame comprises a first sequence of instructions for said plurality of processors coupled to said channels, which instructions instruct said processors as to when to place data on said high speed bus, and each of said plurality of processors synchronously and simultaneously runs said data frame and places data on said high speed bus according to said instructions of said data frame when the channel with which a particular processor is associated is indicated by said data frame. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification