Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels

• US 5,469,444 A
• Filed: 11/16/1994
• Issued: 11/21/1995
• Est. Priority Date: 03/12/1991
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Aritome, Seiichi, Tanaka, Yoshiyuki, Kirisawa, Ryouhei, Tanaka, Tomoharu, Shirota, Riichiro, Endoh, Tetsuo, Ohuchi, Kazunori
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/341,955
• Time in Patent Office: 370 Days
• Field of Search: 371/21.1, 371/21.5, 371/21.6, 371/21.4, 371/21.2, 365/201, 365/184, 365/185
• US Class Current: 714/722
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3413 Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

Claims

1. A non-volatile semiconductor memory system comprising:

an array of rows and columns of memory cells comprising electrically erasable and programmable memory cell transistors;

charge/discharge control means connected to said array, for causing a sub-array of memory cell transistors selected from said array to change a threshold voltage thereof by changing the amount of electrical carriers being charged therein; and

verify means for verifying a resultant electrical state of said sub-array of memory cell transistors by checking their threshold voltages for variations using a first reference voltage and a second reference voltage potentially greater than the first voltage which voltages define a specific range, and for, when an irregular cell transistor remains among them to have an insufficient threshold voltage which is out of the range, performing an additional charge-amount change operation for a predetermined period of time so as to facilitate the state thereof to come closer to the range.

2. A system according to claim 1, wherein said verify means comprises:

read means for reading data from said sub-array to generate a read data;

storage means for receiving an original data to be written into said sub-array, and for holding the original data; and

comparator means connected to said read means and said storage means, for comparing the read data with the original data, and for generating a digital comparison signal.

3. A system according to claim 2, wherein said read means comprises:

voltage supply means associated with said array, for supplying said sub-array with the first reference voltage to cause said read means to obtain a first read data, and for supplying said sub-array with the second reference voltage to cause said read means to obtain a second read data.

4. A system according to claim 3, further comprising:

verify-controller means responsive to said comparator means, for, when the digital comparison signal indicates that the first read data is coincident with said original data, causing said verify means to terminate the additional charge-amount change operation.

5. A system according to claim 4, wherein said verify-controller means causes said sub-array to be locally abandoned at least partially, when the second read data indicates that at least one cell transistor of said sub-array is kept nonconductive with its threshold voltage potentially greater beyond said range.

6. A method for accessing a non-volatile semiconductor memory device including a plurality of programmable and erasable memory cell transistors which are arranged in rows and columns on a substrate, said method comprising the steps of:

causing a sub-array of memory cell transistors selected from said array to change a threshold voltage thereof by changing the amount of electrical carriers being charged therein;

verifying the resultant electrical state of the selected memory cell transistors by checking their threshold voltages for variations using a first reference voltage and a second reference voltage potentially greater than the first voltage which voltages define a specific range, to determine whether or not an irregular cell transistor remains among them to have an insufficient threshold voltage which is potentially out of the range;

performing, when such an irregular cell transistor is found, an additional charge-amount change operation for a predetermined period of time; and

repeating the verifying step and the additional charge-amount changing step until the electrical state thereof falls into said range.

7. A method according to claim 6, wherein said verifying step comprises the steps of:

receiving an original data to be written into said sub-array to hold the original data in a storage unit;

reading data from said sub-array to generate a read data; and

comparing the read data with said original data to generate a digital comparison signal, which is at a first potential level when the first read data is coincident with said original data, and at a second potential level when the second read data is potentially different from said original data.

8. A method according to claim 7, wherein, while the first reference voltage is applied to the sub-array, the repeating step continues when the digital comparison signal is at the second level, and the repeating step is terminated when the digital comparison signal is at the first level.

9. A method according to claim 8, wherein, while the second reference voltage is amplied to said sub-array, when the second read data indicates that at least one cell transistor of said sub-array is kept nonconductive with its threshold voltage potentially greater beyond said range, said sub-array is forced to be regionally abandoned at least partially.

10. A method according to claim 9, further comprising the steps of:

initializing said array of memory cell transistors by supplying thereto a predetermined voltage;

verifying the resultant electrical state of the memory cell transistors by checking their threshold voltages for variations using a third reference voltage, to determine whether or not an irregularly initialized cell transistor remains among them to have an insufficient threshold voltage which potentially less than said third voltage;

performing, when such an irregular cell transistor is found, an additional initialize operation for a pre-determined period of time; and

repeating the verifying step and the additional initializing step until the electrical state thereof becomes identical with said third voltage.

11. A method according to claim 10, wherein the initializing step and the following steps are executed before said writing step.

12. An electrically programmable and erasable read-only memory device comprising:

an array of rows and columns of memory cells each of which includes a field effect transistors having a carrier storage layer and a control gate, said array being divided into a pluraiity of groups each of which includes a plurality of sub-groups which includes a corresponding number of series circuits of memory cell transistors, said sub-arrays having first and second opposite ends;

parallel address-control lines coupled to the rows of field effect transistors at their control gates;

parallel data-transfer lines insulatively crossed with said address-control lines, and associated with said sub-groups;

switch means for electrically connecting selectively said data-transfer lines to said sub-groups at the first ends thereof;

write means for electrically writing a sub-group of series-connected memory cell transistors being selected from sub-groups included in a selected one of said groups; and

verify means for verifying the electrically written state of the selected memory cell transistors by checking their resulting threshold voltages for variations using a first reference voltage and a second reference voltage potentially greater than the first voltage which voltages define an allowable range, and for, when any irregularly written cell transistor remains among them to have an insufficient threshold voltage which is potentially less than the range, performing an additional write operation for a predetermined period of time so that the written state thereof comes closer to a satisfiable state.

13. A device according to claim 12, wherein said verify means comprises:

means connected to said address-control lines, for selectively generating a first and a second direct-current voltages as the first and second reference voltages, the first direct-current voltage defining the lower-limit level of said allowable range, and the second direct-current voltage which defines the upper-limit level of said allowable range and potentially less than a power supply voltage of said memory device.

14. A device according to claim 13, wherein said verify means further comprises:

read means connected to said data-transfer lines, for sequentially reading data from said selected memory cell transistors by using said first and second reference voltages.

15. A device according to claim 14, wherein said verify means further comprises:

data latch means for receiving an original data to be written into said selected memory cell transistors; and

comparator means, coupled to said read means and said data latch means, for comparing a read data with the original data to generate a 1-bit comparison signal.

16. A device according to claim 15, further comprising:

means connected to said verify means and said comparator means, for, when the comparison signal is at a specific logic level indicating that a read data appearing on the corresponding bit line under employment of the first reference voltage is potentially identical with said original data, causing said verify means to terminate the the additional write operation.

17. A device according to claim 16, wherein said array of memory cell transistors comprise floating gate tunneling metal oxide semiconductor (FATMOS) transistors having floating gates for allowing carriers to be selectively accumulated therein.

18. A device according to claim 17, wherein said switch means comprises a plurality of insulated-gate metal insulator semiconductor field effect transistors coupled between said sub-groups of memory cell transistors and said data-transfer lines, respectively.

19. A device according to claim 18, wherein said insulated-gate metal insulator semiconductor field effect transistors have control gates connected together to receive a switch control signal.

20. A device according to claim 19, further comprising:

additional switch means for electrically connecting selectively said sub-groups of memory cell transistors to a fixed potential corresponding to a ground potential at the second ends of said sub-groups, said additional switch means including a plurality of insulated-gate metal insulator semiconductor field effect transistors having gate electrodes connected together to receive a switch control signal.