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Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels

  • US 5,469,444 A
  • Filed: 11/16/1994
  • Issued: 11/21/1995
  • Est. Priority Date: 03/12/1991
  • Status: Expired due to Term
First Claim
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1. A non-volatile semiconductor memory system comprising:

  • an array of rows and columns of memory cells comprising electrically erasable and programmable memory cell transistors;

    charge/discharge control means connected to said array, for causing a sub-array of memory cell transistors selected from said array to change a threshold voltage thereof by changing the amount of electrical carriers being charged therein; and

    verify means for verifying a resultant electrical state of said sub-array of memory cell transistors by checking their threshold voltages for variations using a first reference voltage and a second reference voltage potentially greater than the first voltage which voltages define a specific range, and for, when an irregular cell transistor remains among them to have an insufficient threshold voltage which is out of the range, performing an additional charge-amount change operation for a predetermined period of time so as to facilitate the state thereof to come closer to the range.

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