Event driven power reducing software state machine

• US 5,469,553 A
• Filed: 12/16/1994
• Issued: 11/21/1995
• Est. Priority Date: 04/16/1992
• Status: Expired due to Term

• Current Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Original Assignee: Quantum Corporation (Chi Ko Investment Co., Ltd.)
• Inventors: Patrick, Paul R.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): MOHAMED, AYNI Y
• Application Number:
  US08/357,778
• Time in Patent Office: 340 Days
• Field of Search: 395/375, 395/750, 395/550, 395/775
• US Class Current: 713/323
• CPC Class Codes: G05B 19/042 using digital processors G05B19/05 takes precedence
• CPC Class Codes: G05B 2219/23289 State logic control, finite state, tasks, machine, fsm
• CPC Class Codes: G05B 2219/25291 Set module, component to sleep if no event or no other module needs it
• CPC Class Codes: G05B 2219/25413 Interrupt, event, state change triggered
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: G06F 11/28 by checking the correct order of processing G06F11/08 - G06F11/26 take precedence; monitoring patterns of pulse trains H03K5/19
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

For a computer system or a subsystem thereof having electrical components, a method and apparatus for a collection of event driven software state machine of the type where each state machine is separately operable at differing levels of power consumption, and where the transitions from state to state are as a direct result of input events. Each of the state machines is programmatically biased to operate the state machine at a lowest possible power, and state machines processing event of a higher priority do so at the expense of state machines processing events having a lower priority.

Claims

1. A computer peripheral control system for controlling operations of a computer peripheral device and including a processor for executing instructions and a memory for storing the instructions and a plurality of hardware subsystems of the device being connected to and controlled by said processor, and further comprising:

clock means for driving the processor at a predetermined clock rate;

a plurality of operation software state machines, each of said plurality of operation state machines having a plurality of steady states bridged by transitional states, at least a first one of the steady states being a power reduced steady state and at least a second one of the steady states being a ready steady state, and comprising a sequence of instructions stored in the memory and executed in the processor, and each of said plurality of state machines for operating a corresponding one of the hardware subsystems of the device connected to the processor, an active one of said plurality of operation state machines executing instructions in the processor at a particular time;

event generating means within at least some of the hardware subsystems for generating an event;

event identification means within the processor, responsive to said event, for identifying the event for identifying one the hardware subsystems associated with the event and for identifying one of said plurality of operation state machines to process said event by executing instructions of said at associated operation state machine in the processor, said associated state machine thereupon transitioning through transitional states until a subsequent steady state is reached and operating particular hardware components of said associated one of the hardware subsystems;

said processor including event completion detection means for detecting arrival of said associated state machine at said subsequent steady state,

said associated operation state machine being responsive to the event completion detection means and including a power down transitional slate reached from said subsequent steady state for transitioning said associated operation state machine to the first power reduced steady state for decreasing power to said particular hardware components.

2. The system as in claim 1 wherein said event is a hardware interrupt.

3. The system as in claim 1 wherein said event is a software subroutine call.

4. The system as in claim 2 or 3 further comprising:

means responsive to said event, for saving a context of the processor; and

,

means, responsive to completion of executing instructions to process said event, for restoring said context of the processor.

5. The system as in claim 1 further comprising:

said event completion detection means including timer means for timing a predetermined time period following detection of arrival of said at least one operation state machine at said subsequent steady state and for generating a time-delayed event after expiration of a predetermined time period; and

said at least One operation state machine transitioning through said power down transitional state to reach said power reduced steady state in response to said time-delayed event, for decreasing power to said particular hardware components.

6. The system as in claim 1 wherein said computer peripheral device comprises a hard disk drive of the computer system.

7. The system as in claim 6 wherein said corresponding hardware components include a disk spindle motor and spindle driver chip controlled by a spindle state machine being one of said operation state machines, a bus driver chip controlled by a host state machine being another one of said operation state machines, a servo mechanism including an actuator driver chip and a voice coil actuator and controlled by a servo state machine being a further one of said operation state machines, the hard disk drive including a plurality of circumferentially spaced apart servo spokes recorded on at least one surface of a rotating disk and read by a data transducer head positioned by the voice coil actuator and a read/write driver chip in electrical connection with the data transducer head and controlled by a sector state machines being a still further one of said operation state machines, and where said spindle, host, servo, and sector state machines include transitional states leading to steady states for increasing and decreasing power to operate said corresponding hardware components at controlled power levels.

8. The apparatus as in claim 1 wherein each of said plurality of operation state machines has a priority level and said processor includes means for interrupting instruction execution by said active operation state machine upon receipt of an interrupt corresponding to another one of the operation state machines if said priority level of said active state machine is lower than said priority level of said another one.

9. The apparatus as in claim 1 wherein each said operation state machine further comprises:

a plurality of steady states having instructions for executing in the processor, a first one of said plurality of steady states requiring a first power level to operate said particular hardware components during said first state, and a second one of said plurality of steady states requiting a second power level to operate said particular hardware components during said second state;

transition state means, responsive to processing said event, for transitional said particular state machine from said first steady state to said second steady state; and

power control transition state means, responsive to said transition state means, for controlling said means for increasing and decreasing power to said particular hardware components between said first power level and said second power level.

10. A computer hard disk drive system comprising a base, a data storage disk rotating relative to the base and defining a multiplicity of data tracks interrupted by servo spokes, a rotary voice coil actuator mounted to the base, a data transducer head positioned relative to the data tracks and servo spokes by the rotary voice coil actuator, and an electrical control system mounted to the base and including:

a processor for executing instructions;

clock means for driving the processor at a predetermined clock rate;

a memory for storing said instructions while the processor is executing said instructions;

a spindle motor subsystem for rotating said data storage disk, an actuator control subsystem including the rotary voice coil actuator, a servo spoke subsystem selectively connected to the data transducer head for reading servo head position information recorded in each spoke, and a host interface bus driver circuit and buffer memory subsystem, each said subsystem being coupled to said processor, said plurality of subsystems requiring power to operate;

a plurality of software state machines defined as event driven program structures in said memory using said instructions, each of the plurality of software state machines defining a plurality of steady states bridged by a plurality of transition states, each software state machine including at least a power reduced steady state and a ready steady state, and at least one of said subsystems being associated with each of said plurality of software state machines;

means responsive to said subsystems for generating an event;

means, responsive to said event, for identifying a particular one of said plurality of software state machines to execute said instructions in said processor to process said event;

said particular one of software state machine reaching said a power reduced steady state through a power down transition state responsive to a completion of processing said event, for withdrawing power from said at least one of said plurality of hardware components.