Operating system architecture using multiple priority light weight kernel task based interrupt handling

• US 5,469,571 A
• Filed: 07/15/1991
• Issued: 11/21/1995
• Est. Priority Date: 07/15/1991
• Status: Expired due to Term

• Current Assignee: Lynx Real-Time Systems, Inc.
• Original Assignee: Lynx Real-Time Systems, Inc.
• Inventors: Bunnell, Mitchell
• Primary Examiner(s): Black, Thomas G.
• Assistant Examiner(s): ELLCESSOR, LARR
• Application Number:
  US07/729,942
• Time in Patent Office: 1,590 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 395/650, 395/700, 395/725, 395/600
• US Class Current: 718/103
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A software architecture is implemented through the execution of instructions by a processor. The software architecture provides a first task for performing a first function in response to the occurrence of an interrupt. The first task is assigned a first priority level that is one of a predetermined set of priority levels. A server task is provided to perform a second function in response to the occurrence of the interrupt. The server task is assigned a second priority level that is between predetermined ones of the priority levels of the predetermined set of priority levels. The second priority level is alternately set higher than the first priority level. The operating system kernel includes a scheduler that selects tasks for execution based on relative task priority level. The kernel includes an interrupt handler that provides for setting the server task in a schedulable state in response to the occurrence of the interrupt. The server task, in performance of the second function, provides for setting the first task in a schedulable state with respect to the kernel scheduler so as to allow performance of the first function with respect to the interrupt.

Claims

1. A computer system implementing a software architecture, having a processor to execute instructions providing for controlled responses to occurrences of interrupts, said system comprising:

a) first task means for performing a first function in response to an occurrence of an interrupt, said first task means having a first priority level that is one of a predetermined set of priority levels;

b) interrupt server task means for performing a second function in response to the occurrence of said interrupt, said interrupt server task means having a second priority level that is between predetermined ones of the priority levels of said predetermined set of priority levels, said second priority level being higher than said first priority level; and

c) kernel means for selecting one of a schedulable set of tasks for execution by the processor based upon the relative priority levels of said schedulable set of tasks, said kernel means, responsive to said interrupt, providing for disabling recognition of said interrupt by said kernel means and including said interrupt server task means in said schedulable set of tasks in response to said interrupt, said server task means including means for including said first task means in said schedulable set of tasks.

2. The computer system of claim 1 wherein said kernel means includes means for allocating a kernel data space buffer for said interrupt server task means and a task data space buffer for said first task means to store interrupt data corresponding to said interrupt, wherein said interrupt server task means includes means for transferring the interrupt data to said kernel data space buffer, and wherein said kernel means includes task data transfer means for transferring said interrupt data between said kernel data space buffer and said task data space buffer.

3. The computer system of claim 1 or 2 wherein said interrupt server task means includes means for enabling recognition of said interrupt by said kernel means so that interruption of tasks having a higher priority than said second priority level of said predetermined set of priority levels is limited.

4. A computer system providing for the management of interrupts from multiple interrupt sources within a predetermined bounded interrupt period, said computer system comprising:

a) a processor for executing a program, said processor including an interrupt controller for identifying interrupts originated from a plurality of interrupt sources;

b) a memory storing said program, said program including a plurality of subprograms including a plurality of task subprograms corresponding to said plurality of interrupt sources, each said task subprogram having an associated interrupt handler subprogram and an interrupt server subprogram;

c) scheduling means for controlling the selection of subprograms for execution by said processor, said scheduling means providing for the preemptive execution of said plurality of interrupt handler subprograms in response to respective interrupts and priority based scheduling of said plurality of interrupt server subprograms and said plurality of task subprograms, all but one of said interrupt server subprograms having a priority level less than the priority level of a predetermined task subprogram.

5. The computer system of claim 4 wherein the priority levels of said interrupt server subprograms are interspersed with the priority levels of said task subprograms whereby all but one of said task subprograms has a priority level higher than the priority level of at least one of said interrupt server subprograms.

6. The computer system of claim 5 wherein the said interrupt server subprograms and task subprograms have alternating priority levels.

7. An interrupt control system for managing the execution of a plurality of application tasks in response to the receipt of interrupt signals, said interrupt control system comprising:

a) a processor suitable for the execution of programs; and

b) a memory coupled to said processor,

i) said memory storing a control program and a plurality of application programs, said control program including a scheduling routine, a plurality of interrupt handlers and a plurality of interrupt servers,

ii) said application programs, interrupt handlers and interrupt servers having respective predetermined priority levels,

iii) said scheduling routine providing for the selection of the highest priority level one of a schedulable set of said plurality of application programs and said plurality of interrupt servers,

iv) the predetermined priority levels of said plurality of interrupt handlers being greater than the predetermined priority levels of said plurality of interrupt servers and said plurality of application programs, the priority level of a predetermined one of said interrupt servers being between the priority levels of a predetermined pair of said application programs,

wherein a predetermined interrupt handler is preemptively executed by said processor on receipt of a corresponding interrupt signal, said predetermined interrupt handler disabling recognition of subsequent occurrences of said corresponding interrupt signal and including said predetermined one of said interrupt servers in said schedulable set;

said predetermined one of said interrupt servers providing for the processing of data associated with said corresponding interrupt signal and enabling recognition of subsequent occurrences of said corresponding interrupt signal upon priority scheduled execution of said predetermined one of said interrupt servers.

8. The interrupt control system of claim 7 wherein said predetermined one of said interrupt servers provides for the transfer of data received in connection with said corresponding interrupt signal to a corresponding application program.

9. The interrupt control system of claim 8 wherein said plurality of interrupt servers are implemented as light weight tasks each having a priority level that is greater than the priority level of a respective one of said plurality of application programs and wherein said scheduling routine is executed following execution of each of said plurality of interrupt handlers, said plurality of interrupt servers and application programs.

10. A method of operating a computer system comprising the steps of:

a) selectively scheduling the execution of tasks based on the priority of tasks included in schedulable set of tasks, said tasks including interrupt server tasks and first tasks, where said interrupt server tasks have predetermined priority levels from a first set of priority levels and where said first tasks have predetermined priority levels from a second set of priority levels;

b) preemptively executing an interrupt handler in response to the receipt of an interrupt, the execution of said interrupt handler providing for the inclusion of a predetermined interrupt server task in said schedulable set of tasks;

c) executing said predetermined interrupt server task when said predetermined interrupt server task is priority selected from said schedulable set of tasks for execution, the execution of said predetermined interrupt server task selectively providing for the inclusion of a predetermined first task in said schedulable set of tasks; and

d) executing said predetermined first task when said predetermined first task is priority selected from said schedulable set of tasks for execution, the priority level of said predetermined interrupt server being greater than the priority level of said predetermined first task and less than the priority level of another one of said first tasks.

11. The method of claim 10 wherein the step of executing said interrupt handler includes the step of disabling the receipt of further interrupts corresponding to said interrupt handler and wherein the step of executing said predetermined interrupt server includes the step of enabling the receipt of further interrupts corresponding to said interrupt handler.

12. The method of claim 11 wherein the priority levels of said second set of priority levels are alternatingly interspersed with the priority levels of said first set of priority levels.