Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same

• US 5,470,787 A
• Filed: 05/02/1994
• Issued: 11/28/1995
• Est. Priority Date: 05/02/1994
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Greer, Stuart E.
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/236,320
• Time in Patent Office: 575 Days
• Field of Search: 437/183, 437/182, 437/189, 437/192, 437/193, 437/203, 257/772
• US Class Current: 438/614
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/11502 Pre-existing or pre-deposited material
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13021 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A semiconductor device (32) has an as-deposited solder bump (34) having the intrinsic potential for forming an extended eutectic region for simplified DCA applications. The as-deposited solder bump (34) has first tin layer (40) overlying the UBM of the bonding pad (14) on the device. The first tin layer reacts with a metal layer (36) in the UBM to form an intermetallic for adhering the solder bump to the bonding pad. A thick lead layer (42) overlies the first tin layer to provide the substantial component of the solder bump. A second tin layer (44) overlies the lead layer to provide localized eutectic formation at the top surface of the bump during reflow. A device having at least this solder bump structure can be directly attached to either ceramic or PC board substrates. Additional layers of tin and /or lead may be supplemented to the basic bump structure to optimize the eutectic formation rate.

Claims

1. A method for making a solder bump on a bonding pad of a semiconductor device, comprising the steps of:

providing a first metal layer overlying the bonding pad to provide adhesion of the solder bump to the semiconductor device;

providing a second metal layer overlying the first metal layer;

forming in a vacuum environment a first tin layer overlying the second metal layer, wherein the first tin layer and the second metal layer are mutually soluble such that an intermetallic of the second metal layer and the first tin layer may be formed;

in situ forming a lead layer overlying the first tin layer without breaking the vacuum environment, wherein the lead layer is thicker than the first tin layer; and

forming a second tin layer overlying the lead layer without breaking the vacuum environment, wherein the second tin layer is thinner than the lead layer to provide localized eutectic formation at a top of the solder bump during solder reflow.

2. The method of claim 1, wherein the step of providing the first metal layer comprises providing a metal selected from a group consisting of:

chrome, titanium, and tungsten.

3. The method of claim 1, wherein the step of providing the second metal layer comprises providing a metal selected from a group consisting of:

copper and nickel.

4. The method of claim 1, further comprising the step of providing a third metal layer overlying the second metal layer to prevent the second metal layer from oxidizing, the third metal layer being selected from a group consisting of:

gold, silver, and palladium.

5. The method of claim 1, wherein the step of forming the first tin layer comprises depositing tin in an evaporator, wherein the first tin layer has a thickness approximately in a range of 2,000 to 12,000 angstroms.

6. The method of claim 1, wherein the step of forming the second tin layer comprises evaporating tin to a thickness approximately in a range of 2.5 to 18 microns.

7. The method of claim 1, wherein the step of forming the lead layer comprises evaporating lead to a thickness approximately in a range of 100 to 150 microns.

8. The method of claim 1, further comprising the step of:

depositing, without breaking the vacuum environment, a second lead layer overlying the second tin layer to an approximate ratio of 4 parts lead to 6 parts tin with respect to the second tin layer.

9. The method of claim 1, further comprising the step of:

forming, in the vacuum environment, a second lead layer interposed between the first tin layer and the second metal layer, the second lead layer having an approximate ratio of 4 parts lead to 6 parts tin with respect to the first tin layer.

10. The method of claim 1, further comprising the step of:

exposing the solder bump for a selected time to a temperature approximately in a range of 183°

C. to 225°

C. to form a predefined eutectic region at a surface of the solder bump.

12. The method of claim 1, wherein the step of positioning the semiconductor device is further characterized as positioning the solder bump having a first area overlying and facing a conductive trace having a second area which is approximately in a range of 10% to 20% of the first area.

13. The method of claim 1, wherein the step providing the semiconductor device is further characterized as providing a semiconductor device having a second lead layer interposed between the first tin layer and the second metal layer, the second lead layer being in an approximate ratio of 4 parts lead to 6 parts tin with respect to the first tin layer.

11. A method for performing direct chip attach comprising the steps of:

providing a semiconductor device having a first metal layer overlying a bonding pad to provide adhesion for subsequent metal layers to the semiconductor device, a second metal layer overlying the first metal layer, and a solder bump comprising a first tin layer overlying the second metal layer, wherein the first tin layer and the second metal layer are mutually soluble such that an intermetallic of the second metal layer and the first tin layer may be formed, a lead layer overlying the first tin layer, wherein the lead layer is thicker than the first tin layer, and a second tin layer overlying the lead layer, wherein the second tin layer is thinner than the lead layer to provide localized eutectic formation at a top surface of the solder bump during solder reflow;

positioning the semiconductor device with the solder bump overlying and facing a conductive trace on a mounting substrate;

aligning the solder bump and the conductive trace such that the solder bump is approximately centered over the conductive trace;

bringing the solder bump into physical contact with the conductive trace; and

heating the solder bump to a temperature approximately in a range of 183°

C. to less than 250°

C., wherein a eutectic liquidus solder composed of the second tin layer and a portion of the lead layer is formed at a surface of the solder bump,

wherein the eutectic liquidus solder wets to the conductive trace to join the semiconductor device to the mounting substrate.