Dual-channel emitter switched thyristor with trench gate

• US 5,471,075 A
• Filed: 05/26/1994
• Issued: 11/28/1995
• Est. Priority Date: 05/26/1994
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures Holding 78 LLC (Intellectual Ventures LLC)
• Original Assignee: North Carolina State University (University of North Carolina System)
• Inventors: Shekar, Mallikarjunaswamy S., Baliga, B. Jayant, Korec, Jacek
• Primary Examiner(s): Fahmy, Wael M.
• Application Number:
  US08/249,898
• Time in Patent Office: 551 Days
• Field of Search: 257/147, 257/133, 257/110, 257/155, 257/151, 257/153, 257/138, 257/139, 257/330, 257/331, 257/152, 257/
• US Class Current: 257/139
• CPC Class Codes: H01L 29/0839 Cathode regions of thyristors
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect

Abstract

A semiconductor switching device includes a plurality of adjacent and parallel-connected switching cells in a semiconductor substrate. Each cell includes a thyristor having a floating emitter region and a trench-gate field effect transistor (TFET) for providing turn-on and turn-off control of the thyristor. In one embodiment of the switching device, parasitic thyristor latch-up is suppressed by using a dual-channel TFET which forms both inversion-layer and accumulation-layer channel connections in series between respective floating emitter regions and the cathode contact. In another embodiment, parasitic thyristor latch-up is prevented by joining floating emitter regions of a pair of adjacent cells to thereby eliminate a parasitic P-N-P-N path between the anode and cathode contacts. According to this second embodiment, a dual-channel TFET is preferably used to form a separate first conductivity type inversion-layer channel adjacent a first sidewall of the trench and a second conductivity type inversion-layer channel adjacent a second opposing sidewall of the trench. These channels provide the necessary electrical connections for both gated turn-on and turn-off control.

Claims

1. A semiconductor switching device comprising:

a semiconductor substrate having first and second opposing faces;

a first base region of first conductivity type in said substrate;

an anode region of second conductivity type in said substrate, between said first base region and said first face;

a trench in said substrate at said second face, said trench having a trench sidewall extending adjacent said first base region and a trench bottom;

a floating emitter region of first conductivity type at the bottom of said trench;

a second base region of second conductivity type surrounding said floating emitter region at the bottom of said trench and forming a P-N junction therewith and a P-N junction with said first base region;

a third base region of second conductivity type in said substrate, between said first base region and said second face, said third base region extending adjacent the trench sidewall and forming a P-N junction with said first base region;

a cathode region of first conductivity type in said third base region, said cathode region extending adjacent the trench sidewall;

a cathode contact on the second face, electrically connected to said cathode region, said second base region and said third base region;

an anode contact on the first face, electrically connected to said anode region; and

insulated-gate transistor means, in said substrate, for electrically connecting said cathode region to said first base region in response to a turn-on bias signal, said insulated-gate transistor means comprising a dual-channel field effect transistor having active regions in said first, second and third base regions, a gate electrode in said trench and a gate insulating layer lining said trench so that the trench sidewall defines an interface between said gate insulating layer and said first base region and an interface between said gate insulating layer and said third base region.

2. The semiconductor switching device of claim 1, wherein said second base region extends adjacent the sidewall of said trench so that the trench sidewall defines an interface between said second base region and said gate insulating layer and wherein the application of the turn-on bias signal to said gate electrode electrically connects said cathode region to said first base region by a first inversion-layer channel in said third base region and electrically connects said floating emitter region to said first base region by a second inversion-layer channel in said second base region.

3. The semiconductor switching device of claim 2, wherein the application of the turn-on bias signal to said gate electrode electrically connects the first inversion-layer channel to the second inversion-layer channel in series by an accumulation-layer channel in said first base region.

4. The semiconductor switching device of claim 3, wherein the application of a turn-off bias signal to said gate electrode electrically connects said second base region to said third base region by an inversion-layer channel in said first base region.

5. A semiconductor switching device comprising:

a semiconductor substrate having first and second opposing faces;

a trench in said substrate at said second face;

an anode contact on said first face;

a cathode contact on said second face;

a thyristor between a bottom of said trench and said first face, said thyristor having a floating emitter region of first conductivity type at the trench bottom; and

a dual inversion-layer channel insulated-gate field effect transistor having a gate electrode in said trench, a gate electrode insulating layer extending adjacent a sidewall of said trench, a first active region of first conductivity type in said substrate, opposite said gate electrode insulating layer, and second and third active regions of second conductivity type in said substrate, opposite said gate electrode insulating layer, wherein said first active region extends between said second and third active regions and forms P-N junctions therewith, wherein the application of a turn-on bias signal to said gate electrode electrically connects said floating emitter region to said cathode contact by a first conductivity type inversion-layer channel in said second active region and a first conductivity type inversion-layer channel in said third active region and wherein the application of a turn-off bias signal to said gate electrode electrically connects said third active region to said second active region by a second conductivity type inversion-layer channel in said first active region.

6. A semiconductor switching device comprising:

a semiconductor substrate having first and second opposing faces;

an anode region in said substrate adjacent said first face;

a first base region of first conductivity type in said substrate, on said anode region;

a trench in said substrate at said second face, said trench having a trench bottom and first and second trench sidewalls;

a floating emitter region of first conductivity type and a second base region of second conductivity type at said trench bottom, said second base region extending between said first base region and said floating emitter region and forming P-N junctions therewith; and

a dual inversion-layer channel field effect transistor in said trench, said transistor having first and second conductivity type active regions in said substrate, adjacent the first and second sidewalls of the trench, respectively, wherein said first base region comprises said first conductivity type active region, wherein said second base region comprises said second conductivity type active region, wherein the application of a turn-on gate bias signal to said transistor causes the formation of a first conductivity type inversion-layer channel in said second base region, adjacent the second sidewall, and wherein the application of a turn-off gate bias signal to said transistor causes the formation of a second conductivity type inversion-layer channel in said first base region, adjacent the first sidewall.

7. The semiconductor switching device of claim 6, further comprising

a diverter region of second conductivity type in said substrate, extending adjacent the first sidewall and said second face;

and

a cathode region of first conductivity type in said substrate, extending adjacent the second sidewall and said second face.

8. The semiconductor switching device of claim 6, wherein the application of a turn-on gate bias signal to said dual inversion-layer channel field effect transistor also causes the formation of a first conductivity type inversion-layer channel in the second base region, adjacent the first sidewall and between said floating emitter region and said first base region.

9. A semiconductor switching device comprising:

a semiconductor substrate having first and second opposing faces;

an anode region in said substrate adjacent said first face;

first and second adjacent trenches in said substrate at said second face, and wherein each of said trenches has trench bottoms and first and second trench sidewalls;

a first base region of first conductivity type in said substrate, said first base region extending between said anode region and the first sidewall of said first trench and between said anode region and the first sidewall of said second trench;

first and second overlapping floating emitter regions of first conductivity type at the bottoms of said first and second trenches, respectively;

overlapping second base regions of second conductivity type at the bottoms of said first and second trenches, said overlapping second base regions extending between said first base region and said overlapping floating emitter regions;

a cathode region of first conductivity type on said overlapping second base regions and extending to said second face, said cathode region extending adjacent the second sidewalls of said first and second trenches;

first and second diverter regions of second conductivity type in said substrate which extend adjacent the first sidewalls of said first and second trenches, respectively, and form P-N junctions with said first base region; and

first and second dual inversion-layer channel field effect transistors in said first trench and in said second trench, respectively,

wherein the application of a turn-on gate bias signal to said first and second dual-channel field effect transistors causes the formation of first conductivity type inversion-layer channels adjacent the second sidewalls; and

wherein the application of a turn-off gate bias signal to said first and second dual-channel field effect transistors causes the formation of second conductivity type inversion-layer channels in said first base region and wherein one of said second conductivity type inversion-layer channels extends between said overlapping second base regions and said first diverter region and the other of said second conductivity type inversion-layer channels extends between said overlapping second base regions and said second diverter region.

10. The semiconductor switching device of claim 9, wherein the application of a turn-on gate bias signal to said first and second dual inversion-layer channel field effect transistors causes the formation of first conductivity type inversion-layer channels in the overlapping second base regions, adjacent the first sidewalls.

11. The semiconductor switching device of claim 9, wherein the application of a turn-on gate bias signal to said first and second dual inversion-layer channel field effect transistors causes the formation of first conductivity type inversion-layer channels in the overlapping second base regions, adjacent the second sidewalls.

12. A semiconductor switching device comprising:

a semiconductor substrate having first and second opposing faces;

an anode region in said substrate adjacent said first face;

a first base region of first conductivity type in said substrate, on said anode region;

first and second adjacent trenches in said substrate at said second face, and wherein each of said trenches has trench bottoms and first and second opposing trench sidewalls;

a common floating emitter of first conductivity type at the bottoms of said first and second trenches;

a common second base of second conductivity type surrounding said common floating emitter and forming a P-N junction therewith;

a cathode region of first conductivity type in said substrate, between the second sidewalls of said first and second trenches;

first and second diverter regions of second conductivity type in said substrate, said diverter regions forming P-N junctions with said first base region of first conductivity type and extending adjacent the first sidewalls of said first and second adjacent trenches but not extending adjacent the second sidewalls of said first and second adjacent trenches; and

first and second dual-channel field effect transistors having insulated gate electrodes, in said first trench and in said second trench, respectively, so that the first sidewalls of said first and second trenches define an interface between said insulated gate electrodes and said first base region.

13. The semiconductor switching device of claim 12, wherein the application of a turn-on gate bias signal to said first and second dual-channel field effect transistors causes the formation of first conductivity type inversion-layer channels in the common second base, adjacent the second sidewalls.

14. The semiconductor switching device of claim 12, wherein the application of a turn-off gate bias signal to said first and second dual-channel field effect transistors causes the formation of second conductivity type inversion-layer channels in the first base region, adjacent the first sidewalls of said first and second adjacent trenches.

15. The semiconductor switching device of claim 13, wherein the application of a turn-on gate bias signal to said first and second dual-channel field effect transistors causes the formation of first conductivity type inversion-layer channels in the common second base, adjacent the first sidewalls.

16. An emitter switched thyristor, comprising:

a semiconductor substrate having first and second opposing faces;

anode and cathode contacts on said first and second faces, respectively;

anode and cathode regions of opposite conductivity type in said substrate, adjacent said first and second faces, respectively;

a plurality of adjacent trenches in said substrate, at said second face;

a plurality of electrically insulated gate electrodes in respective ones of said plurality of trenches;

a first base region of same conductivity type as said cathode region in said substrate, said first base region forming a P-N junction with said anode region and extending between adjacent ones of said trenches so that sidewalls of said trenches define a plurality of interfaces between said first base region and said plurality of electrically insulated gate electrodes;

a plurality of floating emitter regions of same conductivity type as said cathode region in said substrate, each of said floating emitter regions extending adjacent a bottom of said plurality of trenches;

a plurality of second base regions of same conductivity type as said anode region in said substrate, each of said second base regions surrounding a respective floating emitter region at a bottom of said plurality of trenches and forming a P-N junction therewith;

a plurality of third base regions of same conductivity type as said anode region in said substrate, each of said third base regions extending between the sidewalls of adjacent ones of said plurality of trenches, forming respective P-N junctions with said first base region and forming respective ohmic contacts with said cathode contact at the second face;

wherein the application of a turn-on bias signal to said plurality of insulated gate electrodes causes the formation of a plurality of first conductivity type inversion-layer channels in said third base regions which electrically connect said first base region to said cathode contact; and

wherein the application of a turn-off bias signal to said plurality of insulated gate electrodes causes the formation of a plurality of second conductivity type inversion-layer channels in said first base region which electrically connect said plurality of second base regions to said plurality of third base regions.

17. The emitter switched thyristor of claim 16, wherein the application of the turn-on bias signal to said plurality of insulated gate electrodes causes the formation of a plurality of first conductivity type inversion-layer channels in said second base regions which electrically connect said first base region to said plurality of floating emitter regions.