Storage element for delay testing

• US 5,471,152 A
• Filed: 10/08/1993
• Issued: 11/28/1995
• Est. Priority Date: 10/08/1993
• Status: Expired due to Fees

• Current Assignee: Duet Technologies, Inc. (Tech Mahindra Limited)
• Original Assignee: CrossCheck Technologies, Inc. (Tech Mahindra Limited)
• Inventors: Varma, Prab, Gheewala, Tushar, Mehta, Rustam
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): BOWSER, BARRY
• Application Number:
  US08/133,588
• Time in Patent Office: 781 Days
• Field of Search: 368/119-120, 324/758, 371/118, 371/76.35, 371/22.1, 371/22.5, 307/308, 326/16, 327/270, 327/271, 327/261, 327/263, 327/278, 327/299, 327/392, 327/202, 327/203
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning

Abstract

A storage element for testing delay paths in integrated circuits is described. The storage element may be used in integrated circuits having matrices of probe and sense lines. The storage element generates a logic transition on an input to a delay path, the logic transition being closely synchronized with a clock signal. The storage element comprises a data input and a data output coupled to the input to the delay path. A master latch receives data from the data input through a first switch, the first switch being controlled by the complement of the clock signal. A slave latch receives data from the master latch through a second switch, the second switch being controlled by the true of the clock signal. A first sense input loads a first logic state into the master latch through a third switch, the first sense input being coupled to one of the IC'"'"'s sense lines. The third switch is controlled by one of the IC'"'"'s probe lines. A second sense input loads a second logic state into the slave latch through a fourth switch, the second sense input being coupled to another one of the IC'"'"'s sense lines. The fourth switch is controlled by a second control signal. The second logic state replaces the first logic state in the slave latch upon application of the clock signal. The desired signal transition is generated where the first logic state is different from the second logic state.

Claims

1. A storage element for generating a logic transition on a delay path input port, the logic transition being closely synchronized with a first control signal, the storage element comprising:

a data input port;

a first switch controlled by the complement of the first control signal;

a master latch coupled to the first switch for receiving data from the data input port through the first switch;

a second switch controlled by the first control signal;

a slave latch coupled to the second switch for receiving data from the master latch through the second switch;

a data output port coupled to the slave latch and the delay path input port;

a third switch controlled by a first probe signal;

a first sense input port coupled to the master latch by means of the third switch, the first sense input port for transmitting a first logic state into the master latch through the third switch, the first sense input port also being coupled to a first sense line;

a fourth switch controlled by a second control signal; and

a second sense input port coupled to the slave latch by means of the fourth switch, the second sense input port for applying a second logic state to the slave latch from outside the storage element through the fourth switch, the second sense input port also being coupled to a second sense line, the second logic state replacing the first logic state in the slave latch upon application of the first control signal, thereby generating the logic transition on the delay path input port where the first logic state is different from the second logic state.

2. A storage element for generating a logic transition in an integrated circuit, the integrated circuit having a matrix of probe lines and sense lines, the storage element generating the logic transition on a delay path input port, the logic transition being closely synchronized with a first control signal, the storage element comprising:

a data input port;

a data output port coupled to the delay path input port;

a first inverter having a first inverter input port and a first inverter output port, the first inverter input port being coupled to the data input port;

a first switch having a first side and a second side, the first switch being controlled by the complement of the first control signal, the first side of the first switch being coupled to the first inverter output port;

a second switch having a first side and a second side, the second switch being controlled by a first probe line, the first side of the second switch being coupled to a first sense line, and the second side of the second switch being coupled to the second side of the first switch;

a second inverter having a second inverter input port and a second inverter output port, the second inverter input port being coupled to the second side of the first switch;

a third inverter having a third inverter input port and a third inverter output port, the third inverter input port being coupled to the second inverter output port;

a third switch having a first side and a second side, the third switch being controlled by the complement of a second probe line, the first side of the third switch being coupled to the third inverter output port;

a fourth switch having a first side and a second side, the fourth switch being controlled by the first control signal, the first side of the fourth switch being coupled to the second side of the third switch, and the second side of the fourth switch being coupled to the second side of the first switch;

a fourth inverter having a fourth inverter input port and a fourth inverter output port, the fourth inverter input port being coupled to the second inverter output port;

a fifth switch having a first side and a second side, the fifth switch being controlled by the first control signal, the first side of the fifth switch being coupled to the fourth inverter output port;

a sixth switch having a first side and a second side, the sixth switch being controlled by a second control signal, the first side of the sixth switch being coupled to a second sense line, and the second side of the sixth switch being coupled to the second side of the fifth switch;

a fifth inverter having a fifth inverter input port and a fifth inverter output port, the fifth inverter input port being coupled to the second side of the fifth switch;

a sixth inverter having a sixth inverter input port and a sixth inverter output port, the sixth inverter input port being coupled to the fifth inverter output port;

a seventh switch having a first side and a second side, the seventh switch being controlled by the complement of the second control signal, the first side of the seventh switch being coupled to the sixth inverter output port;

an eighth switch having a first side and a second side, the eighth switch being controlled by the complement of the first control signal, the first side of the eighth switch being coupled to the second side of the seventh switch, and the second side of the eighth switch being coupled to the second side of the fifth switch; and

a seventh inverter having a seventh inverter input port and a seventh inverter output port, the seventh inverter input port being coupled to the fifth inverter output port, and the seventh inverter output port being coupled to the data output port.

3. A method for generating a logic transition in an integrated circuit, the method employing a storage element comprising a master latch, a slave latch coupled to an input to a delay path, a first sense input port, and a second sense input port, the method comprising the steps of:

transmitting a first logic state into the master latch by means of the first sense input port;

latching the first logic state into the slave latch;

applying a second logic state to the slave latch from outside the storage element by means of the second sense input port; and

causing the logic transition in the slave latch and on the input to the delay path from the first logic state to the second logic state by application of and in close synchronization with a first control signal, the logic transition occurring where the first logic state is different from the second logic state.

5. The method of claim 3 further comprising the steps of:

monitoring a pre-selected point in the delay path to determine when the logic transition has propagated along the delay path to the pre-selected point; and

determining whether the logic transition has propagated to the pre-selected point within a specified period of time.

6. The method of claim 3 further comprising the steps of:

monitoring a pre-selected point in the delay path to determine when the logic transition has propagated along the delay path to the pre-selected point; and

repeating the transmitting, latching, applying, causing, and monitoring-steps, each time decreasing the time between applications of the first control signal until the logic transition at the pre-selected point may no longer be detected before the next application of the first control signal.

4. A storage element for generating a logic transition at an input to a delay path, the logic transition being closely synchronized with a first control signal, the storage element comprising:

a master latch;

a slave latch coupled to the master latch for receiving data from the master latch;

a first sense input port coupled to the master latch for transmitting a first logic state into the master latch;

a second sense input port coupled to the slave latch for applying a second logic state to the slave latch from outside the storage element, the second logic state replacing the first logic state in the slave latch upon application of the first control signal, thereby generating the logic transition in the slave latch where the first logic state is different from the second logic state;

a first switch controlled by the complement of the first control signal;

a data input port coupled to the master latch by means of the first switch through which data may be transmitted from the data input port to the master latch;

a second switch by which the slave latch is coupled to the master latch, and through which data may be transmitted from the master latch to the slave latch, the second switch being controlled by the first control signal;

a third switch by which the first sense input is coupled to the master latch, the third switch being controlled by a first probe signal;

a fourth switch by which the second sense input is coupled to the slave latch, the fourth switch being controlled by a second control signal; and

a data output port coupled to the slave latch and the input to the delay path for transmitting the logic transition to the input to the delay path.