Data signal comparation with self-adjusting threshold

• US 5,471,187 A
• Filed: 09/20/1994
• Issued: 11/28/1995
• Est. Priority Date: 03/10/1993
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Hansen, Jens, Petersen, Jens T., Madsen, Benny
• Primary Examiner(s): Wambach, Margaret Rose
• Application Number:
  US08/309,265
• Time in Patent Office: 434 Days
• Field of Search: 340/146.2, 327/35, 327/175
• US Class Current: 340/146.2
• CPC Class Codes: H03B 2201/0208 the means being an element with a variable capacitance, e.g. capacitance diode
• CPC Class Codes: H03B 5/18 with frequency-determining element comprising distributed inductance and capacitance
• CPC Class Codes: H03C 3/095 applying frequency modulation to the loop in front of the voltage controlled oscillator
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H04B 1/408 the transmitter oscillator frequency being identical to the receiver local oscillator frequency
• CPC Class Codes: H04B 1/56 with provision for simultaneous communication in two directions
• CPC Class Codes: H04L 27/10 Frequency-modulated carrier systems, i.e. using frequency-shift keying H04L27/32 takes precedence
• CPC Class Codes: H04L 27/12 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/148 using filters, including PLL-type filters
• CPC Class Codes: H04L 27/152 using controlled oscillators, e.g. PLL arrangements
• CPC Class Codes: H04L 5/143 for modulated signals H04L5/1469 takes precedence
• CPC Class Codes: H04L 5/1492 with time compression, e.g. operating according to the ping-pong technique

Abstract

A radio frequency (RF) transceiver includes a direct modulation transmitter and single down-conversion receiver for operation in a time-division-duplex (TDD) telecommunications environment. A single RF signal source, in the form of a phase-lock-loop (PLL), is used on a time-shared basis to provide both the carrier signal for the transmitter and the local oscillator (LO) signal for the receiver. In the transmitter, direct modulation is effected by modulating a voltage-controlled oscillator (VCO) in the PLL with a burst of the transmit data while opening the loop and holding the loop feedback tuning voltage constant. In the receiver, a self-adjusting comparator threshold is provided for automatically setting and adjusting a demodulated signal comparison threshold used in retrieving the data and data clock from the demodulated receive signal. The interface between the transmitter and receiver and the host controller provides the control signals needed for the time-sharing of the single RF signal source, the proper programming of the PLL for the different transmitter carrier and receiver LO frequencies, the PLL loop control for the direct modulation of the VCO, and the enablement, or powering down, of the transmitter and receiver sections to minimize transceiver power consumption.

Claims

1. A data signal comparator with a self-adjusting threshold signal for comparing therewith an input signal representing serial data, comprising:

threshold generator means for receiving a threshold control signal and in accordance therewith generating a threshold signal;

input comparator means coupled to said threshold generator means for receiving and comparing said threshold signal and an input signal representing a first plurality of serial binary data bits, and in accordance therewith generating a binary output signal which has an output duty cycle and corresponds to said first plurality of serial binary data bits; and

output monitor means coupled to said input comparator means for receiving and monitoring a temporal characteristic of said binary output signal, and in accordance therewith providing said threshold control signal.

2. A data signal comparator as recited in claim 1, wherein said threshold generator means comprises an adjustable analog voltage generator.

3. A data signal comparator as recited in claim 1, wherein said threshold generator means comprises a digital-to-analog converter.

4. A data signal comparator as recited in claim 1, wherein said input comparator means comprises a voltage comparator, and said threshold signal and said input signal comprise analog voltage signals.

5. A data signal comparator as recited in claim 1, wherein said output monitor means comprises output comparator means for receiving and comparing said binary output signal with a binary reference signal, and in accordance therewith providing said threshold control signal.

6. A data signal comparator with a self-adjusting threshold signal for comparison with an input signal representing serial data, comprising:

a threshold generator which receives a threshold control signal and in accordance therewith generates a threshold signal;

an input comparator, coupled to said threshold generator, which receives and compares said threshold signal and an input signal representing a first plurality of serial binary data bits, and in accordance therewith generates a binary output signal having an output duty cycle and corresponding to said first plurality of serial binary data bits; and

an output monitor, coupled to said input comparator, which receives and monitors a temporal characteristic of said binary output signal, and in accordance therewith provides said threshold control signal.

7. A data signal comparator as recited in claim 6, wherein said threshold generator comprises an adjustable analog voltage generator.

8. A data signal comparator as recited in claim 6, wherein said threshold generator comprises a digital-to-analog converter.

9. A data signal comparator as recited in claim 6, wherein said input comparator comprises a voltage comparator, and said threshold signal and said input signal comprise analog voltage signals.

10. A data signal comparator as recited in claim 6, wherein said output monitor comprises an output comparator which receives and compares said binary output signal with a binary reference signal, and in accordance therewith provides said threshold control signal.

11. A data signal comparison method for adjusting and comparing a threshold signal with an input signal representing serial data, comprising the steps of:

generating a threshold signal;

receiving an input signal representing a first plurality of serial binary data bits;

comparing said threshold signal and said input signal;

generating a binary output signal in accordance with said comparison of said threshold signal and said input signal, wherein said binary output signal has an output duty cycle and corresponds to said first plurality of serial binary data bits;

monitoring a temporal characteristic of said binary output signal; and

selectively adjusting said threshold signal in accordance with said monitoring of a temporal characteristic of said binary output signal.

12. A data signal comparison method as recited in claim 11, wherein said step of generating a threshold signal comprises generating an adjustable analog voltage.

13. A data signal comparison method as recited in claim 11, wherein said step of generating a threshold signal comprises generating an analog voltage with a digital-to-analog converter.

14. A data signal comparison method as recited in claim 11, wherein said threshold signal and said input signal comprise analog voltage signals, and said step of comparing said threshold signal and said input signal comprises comparing said analog voltage signals.

15. A data signal comparison method as recited in claim 11, wherein said step of monitoring a temporal characteristic of said binary output signal comprises comparing said binary output signal with a binary reference signal.

23. A data signal comparison method as recited in claim 11, wherein said step of measuring said binary output signal duty cycle comprises integrating said binary output signal to produce a dc output signal which is proportional to said binary output signal duty cycle.

16. A data signal comparator with a self-adjusting threshold signal for comparing therewith an input signal representing serial data, comprising:

threshold generator means for receiving a threshold control signal and in accordance therewith generating a threshold signal;

input comparator means coupled to said threshold generator means for receiving and comparing said threshold signal and an input signal representing a first plurality of serial binary data bits, and in accordance therewith generating a binary output signal which has an output duty cycle and corresponds to said first plurality of serial binary data bits; and

output monitor means coupled to said input comparator means for receiving and monitoring said binary output signal, and in accordance therewith providing said threshold control signal, wherein said output monitor means comprises a duty cycle monitor for measuring said binary output signal duty cycle and in accordance therewith selectively adjusting said threshold control signal.

17. A data signal comparator as recited in claim 16, wherein said duty cycle monitor comprises an integrator for integrating said binary output signal to produce a dc output signal and in accordance therewith selectively adjusts said threshold control signal.

18. A data signal comparator with a self-adjusting threshold signal for comparing therewith an input signal representing serial data, comprising:

threshold generator means for receiving a threshold control signal and in accordance therewith generating a threshold signal;

input comparator means coupled to said threshold generator means for receiving and comparing said threshold signal and an input signal representing a first plurality of serial binary data bits, and in accordance therewith generating a binary output signal which has an output duty cycle and corresponds to said first plurality of serial binary data bits; and

output monitor means coupled to said input comparator means for receiving and monitoring said binary output signal, and in accordance therewith providing said threshold control signal, wherein said output monitor means comprises output comparator means for receiving and comparing said binary output signal with a binary reference signal, and in accordance therewith providing said threshold control signal, wherein said output comparator means comprises;

a sampler for sampling said binary output signal to provide a binary sample signal which includes a second plurality of logical ones and zeroes; and

a binary comparator coupled to said sampler for receiving and comparing said binary sample signal with said binary reference signal which includes a third plurality of logical ones and zeroes, and in accordance therewith providing said threshold control signal.

19. A data signal comparator with a self-adjusting threshold signal for comparison with an input signal representing serial data, comprising:

a threshold generator which receives a threshold control signal and in accordance therewith generates a threshold signal;

an input comparator, coupled to said threshold generator, which receives and compares said threshold signal and an input signal representing a first plurality of serial binary data bits, and in accordance therewith generates a binary output signal having an output duty cycle and corresponding to said first plurality of serial binary data bits; and

an output monitor, coupled to said input comparator, which receives and monitors said binary output signal, and in accordance therewith provides said threshold control signal, wherein said output monitor comprises a duty cycle monitor which measures said binary output signal duty cycle and in accordance therewith selectively adjusts said threshold control signal.

20. A data signal comparator as recited in claim 19, wherein said duty cycle monitor comprises an integrator which intergrates said binary output signal to produce a dc output signal and in accordance therewith selectively adjusts said threshold control signal.

21. A data signal comparator with a self-adjusting threshold signal for comparison with an input signal representing serial data, comprising:

a threshold generator which receives a threshold control signal and in accordance therewith generates a threshold signal;

an input comparator, coupled to said threshold generator, which receives and compares said threshold signal and an input signal representing a first plurality of serial binary data bits, and in accordance therewith generates a binary output signal having an output duty cycle and corresponding to said first plurality of serial binary data bits; and

an output monitor, coupled to said input comparator, which receives and monitors said binary output signal, and in accordance therewith provides said threshold control signal, wherein said output monitor comprises an output comparator which receives and compares said binary output signal with a binary reference signal, and in accordance therewith provides said threshold control signal, wherein said output comparator comprises;

a sampler which samples said binary output signal to provide a binary sample signal including a second plurality of logical ones and zeroes; and

a binary comparator, coupled to said sampler, which receives and compares said binary sample signal with said binary reference signal which includes a third plurality of logical ones and zeroes, and in accordance therewith provides said threshold control signal.

22. A data signal comparison method for adjusting and comparing a threshold signal with an input signal representing serial data, comprising the steps of:

generating a threshold signal;

receiving an input signal representing a first plurality of serial binary data bits;

comparing said threshold signal and said input signal;

generating a binary output signal in accordance with said comparison of said threshold signal and said input signal, wherein said binary output signal has an output duty cycle and corresponds to said first plurality of serial binary data bits;

monitoring said binary output signal by measuring said binary output signal duty cycle; and

selectively adjusting said threshold signal in accordance with said monitoring of said binary output signal.

24. A data signal comparison method for adjusting and comparing a threshold signal with an input signal representing serial data, comprising the steps of:

generating a threshold signal;

receiving an input signal representing a first plurality of serial binary data bits;

comparing said threshold signal and said input signal;

generating a binary output signal in accordance with said comparison of said threshold signal and said input signal, wherein said binary output signal has an output duty cycle and corresponds to said first plurality of serial binary data bits;

monitoring said binary output signal by comparing said binary output signal with a binary reference signal by sampling said binary output signal to provide a binary sample signal which includes a second plurality of logical ones and zeroes and comparing said binary sample signal with said binary reference signal which includes a third plurality of logical ones and zeroes; and

selectively adjusting said threshold signal in accordance with said monitoring of said binary output signal.