×

Reed-solomon decoder using discrete time delay in power sum computation

  • US 5,471,485 A
  • Filed: 11/24/1992
  • Issued: 11/28/1995
  • Est. Priority Date: 11/24/1992
  • Status: Expired due to Term
First Claim
Patent Images

1. A power sum computation unit for a decoder of a Reed-Solomon code having a redundancy of r symbols and m bits per symbol in which M parallel multipliers operate on M symbols simultaneously to increase computation speed by M over a symbol-serial computation speed, said power sum computation unit comprisingdata input means for sequentially receiving coded symbols,a plurality of exclusive OR gates equal in number to said plurality of multipliers,memory delay means having a bit width equal in number to said number of multipliers times the number of bits per symbol, and a depth equal in number to said redundancy divided by the number of multipliers,said plurality of exclusive OR gates connecting coded symbols to said memory delay means,multiplication means including said M parallel multipliers,gate means for sequentially applying said symbols stored in said memory delay means to said M parallel multipliers,means for providing powers of a finite field element, α

  • , from the power 0 to the power equal in number to one less than the redundancy to said multiplication means, whereby said multiplication means multiplies in parallel M symbols by said powers of said alpha, andmeans for applying the products from said multiplications means to said exclusive OR gates along with coded symbols to provide a power sum output from said exclusive OR gate.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×