Clock fault detection circuit

• US 5,471,488 A
• Filed: 04/05/1994
• Issued: 11/28/1995
• Est. Priority Date: 04/05/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bender, Carl A.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): LE, DIEU MINH T
• Application Number:
  US08/222,813
• Time in Patent Office: 602 Days
• Field of Search: 371/61, 371/20.6, 371/67.1, 371/22.3, 371/4, 371/47.1, 371/2.1, 371/5.1, 371/62, 371/48, 327/291, 327/292, 327/298, 327/299, 327/44, 307/409, 307/413, 375/107
• US Class Current: 714/55
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

An apparatus for transferring data between a main processor and its memory and a packet switch includes a first bus coupled to the main processor and its memory, a bidirectional first-in-first-out (FIFO) buffer coupled between the first bus and a second bus, and having a first port connected to the first bus and a second port connected to the second bus, a communications processor, coupled to the second bus, a memory operatively coupled to the second bus, a first direct memory access (DMA) engine coupled between the first bus and the FIFO buffer for transferring data between the main processor and the FIFO buffer, a second direct memory access (DMA) engine coupled between the FIFO buffer and the second bus for transferring data between the FIFO buffer and the second bus, and a packet switch interface, operatively coupled between the second bus and the switch, for interfacing the second bus to the switch, wherein packets are communicated between the memory of the main processor and the switch in accordance with the communication protocol, and wherein the first and second DMA engines transfer data for the packets independently of each other.

Claims

1. A clock circuit for an adaptor, said adaptor being coupled between a channel of a main processor and a switching mechanism, said clock circuit comprising:

a switch clock located in said switching mechanism, said switch clock having an output coupled to said adaptor, said switch clock generating a clock signal having a first state and a second state;

a counting mechanism in said adaptor including;

a first input connected to an output of said switch clock for sensing transmission of said clock signal from said first state to said second state,

a second input connected to said output of said switch clock the sensing a transition of said clock signal the said second state to said first state,

a counter connected to said first and second inputs for starting counting from an initial value to a terminal value responsive to the sensing of one of the transitions in said clock signal, and

an output for generating a reset signal responsive to said counter counting to said terminal value, a frequency of said counter being greater than that of said clock signal such that a missing clock signal transition allows said counting mechanism to reach said terminal value;

reset means, operatively coupled to said output of said counting mechanism, for resetting said adaptor responsive to said reset signal; and

reset transmitting means, coupled between said reset means and said channel of said main processor, for transmitting a reset condition of said adaptor to said channel, such that said channel avoids being left in a hung condition if a clock signal transition is missed.

2. A clock circuit according to claim 1, wherein said counter comprises first and second counters respectively coupled to said first and second inputs.

3. A clock circuit according to claim 2, wherein said reset means includes an OR gate coupled to said counting mechanism.

4. A clock circuit according to claim 3, wherein said terminal value being reached causes a bus error in said channel.

5. A clock circuit according to claim 3, wherein resetting of said adaptor causes immediate termination of a transaction cycle of data being transferred by said adaptor between said channel and said switching mechanism.

6. A clock circuit according to claim 1, wherein said reset means includes an OR gate coupled to said counting mechanism.

7. A clock circuit according to claim 1, wherein said terminal value being reached causes a bus error in said channel and stops all communication through said channel, and

said switch clock comprising a single phase clock.

8. A clock circuit for an adaptor, said adaptor being coupled between a channel of a main processor and a switching mechanism, said clock circuit comprising:

a switch clock located in said switching mechanism, said switch clock having an output coupled to said adaptor, said switch clock generating a clock signal having a first state and a second state;

a counting mechanism in said adaptor including;

a first input connected to an output of said switch clock for sensing a transition of said clock signal from said first state to said second state,

a second input connected to said output of said switch clock for sensing a transition of said clock signal from said second state to said first state,

a counter connected to said first and second inputs for starting counting from an initial value to a terminal value responsive to the sensing of one of the transitions in said clock signal,

an output for generating a reset signal responsive to said counter counting to said terminal value, a frequency of said counter being greater than that of said clock signal such that a missing clock signal transition allows said counting mechanism to reach said terminal value; and

reset means, operatively coupled to said output of said counting mechanism, for resetting said adaptor responsive to said reset signal, such that said channel avoids being left in a hung condition if a clock signal transition is missed.

9. A clock circuit according to claim 8, further comprising reset transmitting means, coupled between said reset means and said channel of said main processor, for transmitting said reset condition of said adaptor to said channel, such that said channel avoids being left in a hung condition if a clock signal transition is missed.

10. A clock circuit according to claim 8, wherein said counter comprises first and second counters respectively coupled to said first and second inputs.

11. A circuit according to claim 8, wherein said reset means includes an OR gate coupled to said counting mechanism.

12. A clock circuit according to claim 8, wherein resetting of said adaptor causes immediate termination of a transaction cycle of data being transferred by said adaptor between said channel and said switching mechanism.

13. A clock circuit according to claim 8, wherein said reset means includes an OR gate coupled to said counting mechanism.

14. A clock circuit according to claim 8, wherein said terminal value being reached causes a bus error in said channel.

15. A clock circuit for an adaptor, said adaptor being coupled between a channel of a main processor and a switching mechanism, said clock circuit comprising:

a switch clock located in said switching mechanism, said switch clock having an output coupled to said adaptor, said switch clock generating a clock signal having a first state and a second state;

a counting mechanism in said adaptor including;

a first input connected to an output of said switch clock for sensing a transition of said clock signal from said first state to said second state,

a second input connected to said output of said switch clock for sensing a transition of said clock signal from said second state to said first state,

a counter connected to said first and second inputs for starting counting from an initial value to a terminal value responsive to the sensing of one of the transitions in said clock signal,

an output for generating a reset signal responsive to said counter counting to said terminal value, a frequency of said counter being greater than that of said clock signal such that a missing clock signal transition allows said counting mechanism to reach said terminal value; and

reset means, operatively coupled to said output of said counting mechanism, for resetting said adaptor responsive to said reset signal,

wherein said terminal value being reached causes a bus error in said channel and stops all communication through said channel,

said switch clock comprising a single phase clock.

16. A clock circuit for use with an adaptor, said adaptor being coupled between a channel of a microprocessor and a switch clock of a switching mechanism, said clock circuit comprising:

first and second counters for respectively receiving first and second inputs from said switch clock, said first and second counters each being set to a predetermined frequency different from a frequency of said switch clock such that an absence of a signal frequency of said switch clock indicates a missing clock and allows at least one of said first and second counters to reach a predetermined terminal count value; and

reset means, operatively coupled to said adaptor, for resetting said adaptor upon said at least one of said first and second counters reaching said predetermined terminal count value and transmitting a reset condition of said adaptor indicating said adaptor being reset to said channel, such that said channel avoids being left in a hung condition if a clock signal transition is missed.

17. A clock circuit according to claim 16, further comprising reset transmitting means, coupled between said reset means and said processor channel, for transmitting said reset condition of said adaptor to said channel, such that said channel avoids being left in a hung condition if a clock signal transition is missed.

18. A clock circuit according to claim 17, further comprising a local clock, wherein each of said first and second counters is clocked by said local clock independent of said switch clock.

19. A clock circuit according to claim 18, wherein said switch clock is coupled to said reset of said adaptor.

20. A clock circuit according to claim 19, wherein said first counter has a reset having a first predetermined value and said second counter has a reset having a second predetermined value,

wherein, if said switch clock malfunctions at said first predetermined value, said first counter reaches said predetermined terminal count and wherein, if said external clock malfunctions at said second predetermined value, said second counter reaches said predetermined terminal count.

21. A clock fault detection circuit for use with an adaptor, said adaptor being coupled between a channel of a main processor and a switching mechanism, the clock fault detection circuit including:

a clock source external to the adaptor and having an output coupled to said adaptor, the clock source generating a wave having a predetermined shape;

a counting mechanism in the adaptor including;

a first input connected to an output of the clock source for sensing whether the wave has a first predetermined level, a locally generated wave having a predetermined shape and being independent of the clock source,

a second input connected to the output of the clock source for sensing whether the wave has a second predetermined level,

a plurality of counters, clocked by a locally generated wave having a predetermined shape independent or the clock source, and being connected to the first and second inputs for starting counting from an initial value to a terminal value and an output responsive to at least one of the plurality of counters counting to the terminal value, a frequency of the plurality of counters being greater than a frequency of the wave having the predetermined shape such that a missing clock signal transition allows the counting mechanism to reach the terminal value;

a reset device, operatively coupled to said output of the counting mechanism, for resetting the adaptor; and

a reset transmitting device, operatively coupled between the reset device and the main processor, for transmitting the resetting of the adaptor to the main processor, such that the main processor avoids being left in a hung condition if a clock signal transition is missed.

22. A clock fault detection circuit according to claim 21, wherein said predetermined shape of said wave generated by said external source clock and that of said locally generated wave is rectangular.

23. A clock fault detection circuit according to claim 22, wherein said first predetermined level has a value greater than a value of said second predetermined level.