Multi-processor with crossbar link of processors and memories and method of operation

• US 5,471,592 A
• Filed: 06/21/1994
• Issued: 11/28/1995
• Est. Priority Date: 11/17/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ing-Simmons, Nicholas K., Guttag, Karl M., Balmer, Keith, Gove, Robert J.
• Primary Examiner(s): Ray, Gopal C.
• Assistant Examiner(s): Sheikh, Ayaz R.
• Application Number:
  US08/263,504
• Time in Patent Office: 525 Days
• Field of Search: 395/325, 395/725, 395/425
• US Class Current: 709/213
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring

Abstract

There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories, are contained on a single silicon chip.

Claims

1. A method of operating a multiprocessing system having processors, said processors generating addresses within a predetermined range of addresses and operable from instruction streams provided from memories each having a unique addressable memory spaces, said unique addressable memory space of each of said memories being separate and distinct from said unique addressable space of any other of said memories and said unique addressable memory space of each of said m memories being within said predetermined range of addresses of said n processors, so that instructions are executed by said processors, said method comprising the steps of:

selectively and concurrently interconnecting via a switch matrix any of said processors with any of said memories to establish selective interconnections for the communication over said selective interconnections of instructions from one or more of said addressable memory spaces and data from other of said addressable memory spaces;

wherein said switch matrix contains a plurality of crosspoints and wherein said method further comprises operating at least one of said processors to provide an address;

controlling each of said crosspoints in response to the address thus provided to connect one of the memories having said address generated by one of said processors in its unique addressable memory space to only the processor which provided that address thereby to pass both address and data through the same crosspoint to said one of the memories;

establishing a priority for accessing when more than one of said n processors attempts to access any particular one memory in said m memories, a processor making a last successful access to said particular one memory assigned a lowest priority; and

changing said selective interconnection between said processors and said memories on a processor cycle-by-cycle basis.

2. The method set forth in claim 1 further comprising the step of reducing contention for memory by distributing data to be used by different ones of said processors to different ones of said memories.

3. The method set forth in claim 1 further comprising the step of reducing contention for memory by loading instructions for the processors which instructions are coded to cause each processor to access a particular memory respective to it so that the processors concurrently access different memories respective to each of them.

4. The method set forth in claim 1 wherein said prioritization system includes sequential token passing granting processor access to a particular one of said m memories in a predetermined sequence when more than one of said n processors simultaneously generate addresses within said unique addressable memory space of said particular memory.

5. The method set forth in claim 4 further comprising the step of:

selectively and concurrently interconnecting via a switch matrix a separate processor with any of said memories to establish selective interconnections for the communication over said selective interconnections of instructions from one or more of said addressable memory spaces and data from other of said addressable memory spaces; and

wherein said step of sequencing simultaneous processor access attempts to the same memory further includes the step of giving lowest priority to said separate processor for each said memory.

6. A multi-processing system comprising:

n processors;

m memories each having a unique addressable memory space, and wherein m is greater than n, each of said processors generating addresses within a predetermined range of addresses and operable from instruction sets provided from at least one of said memories for controlling a number of different processes, said unique addressable memory space of each of said m memories being separate and distinct from said unique addressable space of any other of said m memories and said unique addressable memory space of each of said m memories being within said predetermined range of addresses of said n processors;

a switch matrix connected to said memories and connected to said processors to selectively route both addresses and data from said processors to said memories via the switch matrix, said switch matrix including contention circuitry connected to said n processors and establishing a priority for accessing when more than one of said n processors attempts to access any particular one memory in said m memories, said contention circuitry assigning a lowest priority to a processor making a last successful access to said particular one memory; and

circuitry responsive to said addresses from each of said n processors for selectively transferring said addresses generated by one of said processors and data through said switch matrix between only said processor generating said address and a one of said m memories having said unique addressable memory space including said address on a processor cycle by cycle basis for interconnecting any of said n processors with any of said m memories for communication between said memories and said connected processors of data from one or more of the addressable memory spaces and data from at least another of the addressable memory spaces.

7. The system set forth in claim 6 wherein:

said contention circuitry further includes sequential token passing circuitry for granting processor access to a particular one of said m memories in a predetermined sequence when more than one of said n processors simultaneously generate addresses within said unique addressable memory space of said particular memory.

8. A multi-processing system comprising:

an external address/data port adapted for connection to an apparatus external to said multi-processing system;

n processors;

m memories each having a unique addressable memory space, and wherein m is greater than n, each of said n processors generating addresses within a predetermined range of addresses and operable from instruction sets provided from at least one of said memories for controlling a number of different processes, said unique addressable memory space of each of said m memories being separate and distinct from said unique addressable space of any other of said m memories and said unique addressable memory space of each of said m memories being within said predetermined range of addresses of said n processors;

a transfer processor connected to said external address/data port for transferring data between said multi-processing system and said apparatus external to said multi-processing system;

a switch matrix connected to said memories and connected to said n processors and said transfer processor for selectively route both addresses and data from said n processors and said transfer processor to said memories via the switch matrix; and

circuitry responsive to said addresses from each of said n processors and said transfer processor for selectively transferring said addresses generated by one of said n processors or said transfer processor and data through said switch matrix between only said one of said n processors or said transfer processor generating said address and a one of said m memories having said unique addressable memory space including said address on a processor cycle by cycle basis for interconnecting any of said n processors with any of said m memories for communication between said memories and said connected processors of data from one or more of the addressable memory spaces and data from at least another of the addressable memory spaces;

contention circuitry connected to said n processors and said transfer processor and establishing a priority for accessing when more than one of said n processors attempts to access any particular one memory in said m memories, said contention circuitry assigning a lowest priority to said transfer processor.

9. The system set forth in claim 8 wherein said transfer processor controls data transfer between said m memories and said apparatus external to said multi-processing system in response to instructions from said n processors.

10. A method of operating a multi-processing system having processors, said processors generating addresses within a predetermined range of addresses and operable from instruction streams provided from memories each having a unique addressable memory spaces, said unique addressable memory space of each of said memories being separate and distinct from said unique addressable space of any other of said memories and said unique addressable memory space of each of said m memories being within said predetermined range of addresses of said n processors, so that instructions are executed by said processors, said method comprising the steps of:

selectively and concurrently interconnecting via a switch matrix any of said processors with any of said memories to establish selective interconnections for the communication over said selective interconnections of instructions from one or more of said addressable memory spaces and data from other of said addressable memory spaces;

wherein said switch matrix contains a plurality of crosspoints and wherein said method further comprises operating at least one of said processors to provide an address;

controlling each of said crosspoints in response to the address thus provided to connect one of the memories having said address generated by one of said processors in its unique addressable memory space to only the processor which provided that address thereby to pass both address and data through the same crosspoint to said one of the memories;

changing said selective interconnection between said processors and said memories on a processor cycle-by-cycle basis; and

transferring data between one of said m memories and an apparatus external to said multi-processing system at a priority lower than all other processor access to said m memories.

11. The method set forth in claim 10 further comprising the step of reducing contention for memory by distributing data to be used by different ones of said processors to different ones of said memories.

12. The method set forth in claim 10 further comprising the step of reducing contention for memory by loading instruction for the processors which instructions are coded to cause each processor to access a particular memory respective to it so that the processors concurrently access different memories respective to each of them.