×

Multi-processor with crossbar link of processors and memories and method of operation

  • US 5,471,592 A
  • Filed: 06/21/1994
  • Issued: 11/28/1995
  • Est. Priority Date: 11/17/1989
  • Status: Expired due to Term
First Claim
Patent Images

1. A method of operating a multiprocessing system having processors, said processors generating addresses within a predetermined range of addresses and operable from instruction streams provided from memories each having a unique addressable memory spaces, said unique addressable memory space of each of said memories being separate and distinct from said unique addressable space of any other of said memories and said unique addressable memory space of each of said m memories being within said predetermined range of addresses of said n processors, so that instructions are executed by said processors, said method comprising the steps of:

  • selectively and concurrently interconnecting via a switch matrix any of said processors with any of said memories to establish selective interconnections for the communication over said selective interconnections of instructions from one or more of said addressable memory spaces and data from other of said addressable memory spaces;

    wherein said switch matrix contains a plurality of crosspoints and wherein said method further comprises operating at least one of said processors to provide an address;

    controlling each of said crosspoints in response to the address thus provided to connect one of the memories having said address generated by one of said processors in its unique addressable memory space to only the processor which provided that address thereby to pass both address and data through the same crosspoint to said one of the memories;

    establishing a priority for accessing when more than one of said n processors attempts to access any particular one memory in said m memories, a processor making a last successful access to said particular one memory assigned a lowest priority; and

    changing said selective interconnection between said processors and said memories on a processor cycle-by-cycle basis.

View all claims
  • 0 Assignments
Timeline View
Assignment View
    ×
    ×