Computer processor with an efficient means of executing many instructions simultaneously

• US 5,471,593 A
• Filed: 01/21/1994
• Issued: 11/28/1995
• Est. Priority Date: 12/11/1989
• Status: Expired due to Term

• Current Assignee: Microprocessor Enhancement Corporation (Acacia Research Corporation)
• Original Assignee: Michael H Branigin
• Inventors: Branigin, Michael H.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): MOHAMED, AYNI Y
• Application Number:
  US08/184,355
• Time in Patent Office: 676 Days
• Field of Search: 395/375
• US Class Current: 712/235
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30069 Instruction skipping instructions, e.g. SKIP
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag

Abstract

To increase the performance of a pipelined processor executing instructions, conditional instruction execution issues and executes instructions, including but not limited to branches, before the controlling conditions may be available and makes the decision to update the destination as late as possible in the pipeline. Conditional instruction execution is further improved by a condition code mask field in instructions to choose those condition code bits to be involved in the decision; by a set condition code flag to enable or disable the setting of a condition code; by stale condition code handling to determine if the logically previous conditionally executing instruction was successful or unsuccessful in setting the condition code and to conditionally execute accordingly; by multiple condition codes so that independent instruction sequences can use condition codes in parallel; and by condition code reservation stations to capture a needed condition code as soon as it becomes available and hold that captured value until needed, thus freeing the condition code as soon as possible for use by other instructions. Moving the conditional decision from the point of instruction issue to the point of instruction completion permits branch instructions to be eliminated in many cases; permits conditionally executing instructions directly in line; permits filling the branch umbra following a delayed branch with conditionally executing instructions; and reduces the latency from condition code generation to condition code use.

Claims

1. A method of executing instructions in a pipelined processor comprising:

a conditional execution decision logic pipeline stage and a least one instruction execution pipeline stage prior to said conditional execution decision logic pipeline stage;

at least one condition code;

said instructions including branch instructions and non-branch instructions and each instruction including opcodes specifying operations, operand specifiers specifying operands, and conditional execution specifiers;

said pipelined processor further including at least one write pipeline stage for writing the result(s) of each instruction to specified destination(s);

at least one of the instructions including a means for specifying writing said condition code with a condition code result;

the conditional execution decision logic pipeline stage performing a boolean algebraic evaluation of the condition code and said conditional execution specifier and producing an enable-write with at least two states, true and false; and

said enable-write when true enabling and when those disabling the writing of instruction results at said write pipeline stage;

said method further comprising the steps of;

fetching source operands specified by said operand specifiers;

performing the operation specified by said opcode;

fetching the condition code, when specified by the conditional execution specifier, at the pipeline stage immediately preceding the conditional execution decision logic pipeline stage;

operating the conditional execution decision logic pipeline stage, when specified by the conditional execution specifier, to determine the enable-write using the boolean algebraic evaluation;

writing said non-branch instruction results to a destination specified by the operand specifiers of the executing instruction and writing condition code results to the condition code when specified by the operand specifiers of the executing instruction, if the enable-write is true; and

discarding or not writing the non-branch instruction results and discarding or not writing the condition code, if the enable-write is false.

2. The method as claimed in claim 1, wherein the conditional execution specifier includes a mask field;

each bit of said mask field selecting a corresponding bit in the condition code for inclusion in the boolean algebraic evaluation.

3. The method as claimed in claim 1, wherein the instructions include a set condition code flag with two states:

a set-state for enabling the writing of the condition code, when also enabled by the true enable-write; and

a no-set-state for disabling writing to the condition code.

4. The method as claimed in claim 1, wherein:

the condition code includes a good-or-stale indicator;

the conditional execution specifier includes a good-or-stale specifier;

the boolean algebraic evaluation further including both said good-or-stale indicator and said good-or-stale specifier

the good-or-stale indicator having two states;

a good-state set by an instruction which specifies writing to the condition code and which is enabled by the true enable-write; and

a stale-state set by an instruction which specifies writing to the condition code and which is disabled by the false enable-write;

the conditional execution specifier choosing from a group comprising;

the boolean algebraic includes the good-or-stale indicator and excludes additional condition code bits;

the boolean algebraic evaluation includes the good-or-stale indicator and includes with at least one additional condition code bit; and

the boolean algebraic evaluation excludes the good-or-stale indicator.

5. The method as claimed in claim 1, wherein there is a plurality of condition codes and the instructions include condition code specifiers for selecting one of the condition codes for use in the conditional execution decision.

6. The method as claimed in claim 1, wherein

fetching of the condition code is done in a plurality of pipeline positions as a condition code copy;

said condition code copy is held until needed by the conditional execution decision logic; and

after the condition code copy is fetched, the condition code is freed for use by other instructions.

7. A pipelined processor for executing instructions comprising:

a conditional execution decision logic pipeline stage, a least one instruction execution pipeline stage prior to said conditional execution decision logic pipeline stage;

at least one condition code;

said instructions including branch instructions and non-branch instructions and including opcodes specifying operations, operand specifiers specifying operands, and conditional execution specifiers;

the pipelined processor further including at least one write pipeline stage for writing the result(s) of each instruction to specified destination(s);

at least one of the instructions including a means for specifying writing said condition code with a condition code result;

the conditional execution decision logic pipeline stage performing a boolean algebraic evaluation of the condition code and said conditional execution specifier and producing an enable-write with at least two states, true and false;

said enable-write when true enabling and when false disabling the writing of instruction results at said write pipeline stage;

fetching means for fetching source operands specified by said operand specifiers;

operating means for performing the operation specified by said opcode;

condition code fetching means for fetching the condition code, when specified by the conditional execution specifier, at the pipeline stage immediately preceding the conditional execution decision logic;

the conditional execution decision logic pipeline stage, when specified by the conditional execution specifier, determining the enable-write using the boolean algebraic evaluation;

writing means for writing said non-branch instruction results to a destination specified by the operand specifiers and writing to the condition code when specified, if enable-write is true; and

said writing means further for discarding or not writing the non-branch instruction results and discarding or not writing the condition code, if enable-write is false.

8. The pipelined processor as claimed in claim 7, wherein the conditional execution specifier includes a mask field;

each bit of said mask field selecting a corresponding bit in the condition code for inclusion in the boolean algebraic evaluation.

9. The pipelined processor as claimed in claim 7, wherein the instructions include a set condition code flag with two states:

a set-state for enabling the writing of the condition code, when also enabled by the true enable-write; and

a no-set-state for disabling writing to the condition code.

10. The pipelined processor as claimed in claim 7, wherein:

the condition code includes a good-or-stale indicator;

the conditional execution specifier includes a good-or-stale specifier;

the boolean algebraic evaluation further including both said good-or-stale indicator and said good-or-stale specifier

the good-or-stale indicator having two states;

a good-state set by an instruction which specifies writing to the condition code and which is enabled by the true enable-write; and

a stale-state set by an instruction which specifies writing to the condition code and which is disabled by the false enable-write;

the conditional execution specifier choosing from a group comprising;

the boolean algebraic includes the good-or-stale indicator and excludes additional condition code bits;

the boolean algebraic evaluation includes the good-or-stale indicator and includes with at least one additional condition code bit; and

the boolean algebraic evaluation excludes the good-or-stale indicator.

11. The pipelined processor as claimed in claim 7, wherein there is a plurality of condition codes and the instructions include condition code specifiers for selecting one of the condition codes for use in the conditional execution decision.

12. The pipelined processor as claimed in claim 7, wherein

fetching of the condition code is done in a plurality of pipeline positions as a condition code copy;

said condition code copy is held until needed by the conditional execution decision logic; and

after the condition code copy is fetched, the condition code is freed for use by other instructions.