Modular high-capacity solid-state mass data storage device including controller/memory modules arranged in parallel channels

• US 5,471,603 A
• Filed: 10/19/1992
• Issued: 11/28/1995
• Est. Priority Date: 08/12/1991
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: TRW Inc. (Northrop Grumman Corporation)
• Inventors: Upton, Eric L., Enyedy, Arthur G., Yokote, Timothy A., Brandis, Dirk K., Stockton, Grant J.
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US07/963,192
• Time in Patent Office: 1,135 Days
• Field of Search: 395/425, 395/500, 395/800, 371/21.1, 371/21.2, 371/10.1, 371/10.2, 371/68.1, 371/68.2, 371/68.3, 364/424.04, 364/424.06, 365/200
• US Class Current: 711/2
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A modular solid-state mass data storage device providing high-density, high-capacity storage of data employs a modular pipeline architecture in which a distributed array of controller/memory modules is arranged in parallel controller/memory channels on one or more controller/memory cards, each controller/memory channel having first and last controller/memory modules. The modular storage device also includes a data format module, and first and second busses connecting outputs of the data format module to inputs of each of the first and last controller/memory modules. The first bus also connects outputs of the last controller/memory module in each channel back to an input of the data format modules. The modular pipeline architecture allows the number of controller/memory modules in each channel to be easily configured to accommodate any required storage size, while the number of controller/memory channels can be configured to accommodate any required storage size and transfer rate, without increasing latency time. The modular pipeline architecture also greatly simplifies the complexity of the memory controllers, and high-density packaging of the controller/memory modules provides compact storage for large amounts of data. The mass data storage device may be used as a random access memory (RAM) disk or for any other application requiring high-density, high-capacity mass data storage devices.

Claims

1. A modular solid-state mass data storage device providing high-density, high capacity storage of data, comprising:

first and second parallel controller/memory channels, each including first and last controller/memory modules;

a data format module;

first and second busses connecting outputs of said data format module to inputs of each of said first and last controller/memory modules, the first bus also connecting outputs of the last controller/memory module in each channel back to an input of the data format module,

wherein each controller/memory module includes a memory controller coupled to an array of random access memory chips, and

wherein each memory controller performs at least one of addressing said RAM chips for a read operation, addressing said RAM chips for a write operation, and refreshing said RAM chips.

2. The mass data storage device as set forth in claim 1, wherein the data format module provides data formatting, synchronization and error correction for data stored in the controller/memory modules.

3. The mass data storage device as set forth in claim 1, wherein each RAM chip is connected to a memory controller and the memory controller is connected to the other memory controllers in the same channel by the first and second buses.

4. The mass data storage device as set forth in claim 3, wherein the first bus includes a read data bus and the second bus includes a read address bus, a write address bus, a write data bus and a control bus.

5. The mass data storage device as set forth in claim 4, wherein during said write operation, write addresses on the write address bus and write data on the write data bus are clocked through the memory controllers in one of said controller/memory channels until one of said write addresses matches a write location, and wherein the write data is then written into the write location in one of said RAM chips.

6. The mass data storage device as set forth in claim 4, wherein during said read operation, read addresses on the read address bus are clocked through the memory controller in one of said controller/memory channels until one of said read addresses matches a read location, and wherein read data in one of said RAM chips identified by said one of said read addresses is retrieved and then clocked through the remaining memory controllers in said one of said controller/memory channels on the read data bus back to the data format module.

7. The mass data storage device as set forth in claim 1, wherein the mass data storage device is configured as a random access memory (RAM) disk which emulates a hard disk.

8. The mass data storage device as set forth in claim 7, wherein the mass data storage device includes four controller/memory channels and each controller/memory module has a memory capacity of 16 megabytes (Mbytes).

9. The mass data storage device as set forth in claim 8, wherein every four parallel controller/memory modules are packaged in a single in-line memory module.

10. The mass data storage device as set forth in claim 7, wherein the mass data storage device includes eight controller/memory channels and each controller/memory module has a capacity of 16 Mbytes.

11. The mass data storage device as set forth in claim 10, wherein every four parallel controller/memory modules are packaged in a single in-line memory module.