Methods and apparatus pulse-width modulation that use a counter and a modulus device

• US 5,471,635 A
• Filed: 05/31/1994
• Issued: 11/28/1995
• Est. Priority Date: 06/06/1990
• Status: Expired due to Term

• Current Assignee: NEC Electronics Incorporated (NEC Corporation)
• Original Assignee: NEC Electronics Incorporated (NEC Corporation)
• Inventors: Williams, Stephen R.
• Primary Examiner(s): GECKIL, MEHMET B
• Application Number:
  US08/251,802
• Time in Patent Office: 546 Days
• Field of Search: 395/550, 395/800, 395/725, 364/724.14, 364/749, 364/843, 364/851, 364/858, 364/718
• US Class Current: 713/500
• CPC Class Codes: G06F 1/025 for functions having two-valued amplitude, e.g. Walsh functions
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency

Abstract

Methods are provided for generating a square wave of variable duty cycle using a microprocessor and an interval timer. The duty cycle can be changed without changing the period. The duty cycle is changed on a rising or a falling edge of the signal as desired.

Claims

1. A method of generating a 2-level square wave signal of a predetermined period and a predetermined non-50% duty cycle on an output lead of a circuit which includes a processor including a timer, the method comprising the computer-implemented steps of:

determining from said predetermined period and said duty cycle a duration of a first-level portion of said square wave signal and a duration of a second-level portion of said square wave signal, the duration of the first-level portion being different from the duration of the second-level portion;

determining from the duration of the first-level portion a first number which is a number of cycles of a clock signal in the first-level portion of said square wave signal, and determining from the duration of the second-level portion a second number which is a number of cycles of the clock signal in the second-level portion of said square wave signal, wherein said second number of cycles is different from said first number of cycles;

before loading any one of the first and second numbers into a counter that counts on every cycle of the clock signal, decrementing each of the first and second numbers by a number of cycles required to load a value from a modulus device into the counter;

generating an interrupt signal to the processor when the counter reaches a selected final value;

in response to said interrupt signal, performing the steps of;

if a signal on said output lead is of a first level, then changing the signal on said output lead to a second level different from said first level; and

if the signal on said output lead is of said second level, then changing the signal on said output lead to said first level; and

loading the value from the modulus device into said counter;

following the above steps, counting by said counter towards said final value;

in response to said interrupt signal, after said level changing step but before said counter reaches said final value, and while said counter counts towards said final value, leading by said processor said modulus device with;

said first number of clock cycles if said signal is of said second level; and

said second number of clock cycles if said signal is not of said second level; and

repeating the step of generating the interrupt signal and the step of changing the signal on said output lead thereby generating on the output lead the signal having the non-50% duty cycle.

2. A device for generating a 2-level square wave signal of a predetermined period and a predetermined non-50% duty cycle, comprising:

a computer processor comprising;

an output lead for providing thereon said square wave signal;

a counter;

means for providing a clock signal to the counter to cause the counter to count on every cycle of the clock signal and;

a modulus device;

means for determining from said period and said duty cycle a duration of a first-level portion of said square wave signal and a duration of a second-level portion of said square wave signal, the duration of the first-level portion being different from the duration of the second-level portion;

means for determining from the duration of the first-level portion a first number which is a number of cycles of the clock signal in the first-level portion of said square wave signal, and for determining from the duration of the second-level portion a second number which is a number of cycles of the clock signal in the second-level portion of said square wave signal, wherein said second number of cycles is different from said first number of cycles;

means for decrementing each of the first and second numbers, before loading any one of the first and second numbers into the counter, by a number of cycles required to load a value from the modulus device into the counter;

said computer processor further comprising;

means for generating an interrupt signal when said counter reaches a selected final value;

means responsive to said generating means, for changing said square wave signal on said output lead to a second level if said square wave signal is of a first level, and to said first level if said square wave signal is of said second level;

means responsive to said generating means, for loading a value from said modulus device into said counter in response to said interrupt signal; and

means responsive to said changing means and said loading means, for counting by said counter to said final value; and

means, which comprises an interrupt service routine and is responsive to said interrupt signal, for loading said modulus device, before said counter counts to said final value and while said counter counts towards said final value, with;

said first number of clock cycles if said square wave signal is of said second level; and

said second number of clock cycles if said square wave signal is of said first level, to provide on the output lead the square wave signal of the non-50% duty cycle.

3. The device of claim 2 wherein the computer processor is a microprocessor.