Differential DC offset compensation circuit

• US 5,471,665 A
• Filed: 10/18/1994
• Issued: 11/28/1995
• Est. Priority Date: 10/18/1994
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Pace, Gary L., Hughes, James D.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US08/324,634
• Time in Patent Office: 406 Days
• Field of Search: 330/9, 330/259, 327/307, 455/208, 455/209, 455/278.1, 455/343
• US Class Current: 455/343.2
• CPC Class Codes: H03D 3/008 Compensating DC offsets
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H03F 3/45085 Long tailed pairs H03F3/45112, H03F3/45139 take precedence
• CPC Class Codes: H03F 3/45511 Controlling the loading circuit of the differential amplifier
• CPC Class Codes: H03F 3/45973 by using a feedback circuit
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

A differential direct current (DC) offset compensation circuit for providing DC offset compensation to a circuit device (110). The DC offset compensation circuit (100) comprises a differential integrator (120) and a summing network (130). The circuit device (110) is one of several types of devices, such as a DC coupled amplifier. The differential input (112) of the circuit device (110) is suitable for coupling to a differential input source (140) and the differential output (114) of the circuit device is suitable for connection to a load (150). The differential integrator (120) features a transconductance amplifier (18) at least one other amplifier (13), and a capacitor element (16) having a capacitance of C1. The summing network (130) sums the differential integrator output with the differential input signals of the differential input source (140) and cancels DC offsets of the differential input source (140) and the circuit device (110).

Claims

1. In combination, a receiver circuit for receiving a signal detected by an antenna, and a control circuit for controlling ON and OFF time of the receiver circuit, the receiver circuit comprising:

a radio frequency (RF) amplifier coupled to the antenna for amplifying the signal detected by the antenna and generating an amplified signal;

a mixer coupled to the RF amplifier for mixing the amplified signal with an oscillator signal of a predetermined frequency and generating at an output a mixed signal;

an amplifier stage coupled to the mixer comprising;

a first amplifier coupled to the output of the mixer for amplifying the mixed signal and generating at an output a first differential amplified signal;

a second amplifier DC coupled to the output of the first amplifier and having a predetermined frequency pass characteristic for amplifying the differential amplified signal and for generating at an output a second differential amplified signal;

a differential integrator coupled to the output of the second amplifier for receiving as input the second differential amplified signal and generating at an output a differential integrator output; and

a summing network coupled to the output of the differential integrator and to the output of the first amplifier, the summing network summing the differential integrator output with the first differential amplified signal for canceling any DC offsets of the first amplifier and the second amplifier;

wherein the control circuit generates a receiver power control signal comprising a receiver ON time interval for turning ON the RF amplifier, mixer and amplifier stage, and a receiver OFF time interval for turning OFF the RF amplifier, mixer and amplifier stage.

2. The combination of claim 1, wherein the second amplifier of the amplifier stage is a transimpedance amplifier having a low pass filter characteristic.

3. The combination of claim 1, wherein the first amplifier of the amplifier stage is a transconductance amplifier.

4. The combination of claim 1, wherein the differential integrator comprises an integrator reset, and wherein the control circuit generates an integrator reset control signal for resetting the differential integrator beginning a predetermined time period prior to an end of the receiver OFF time interval, and ending at a beginning of the receiver ON time interval.

5. The combination of claim 1, wherein the differential integrator comprises an integrator reset, and wherein the control circuit generates an integrator reset control signal for resetting the differential integrator for a predetermined time period beginning at the receiver ON time interval.

6. The combination of claim 1, wherein the differential integrator comprises an integrator reset, and wherein the control circuit generates an integrator reset control signal for resetting the differential integrator for a predetermined time period beginning prior to an end of the receiver OFF time interval, and ending a predetermined time period after a beginning of the receiver ON time interval.

7. The combination of claim 1, wherein the differential integrator has an adjustable integrator gain, and wherein the control circuit generates an integrator gain control signal for setting the adjustable integrator gain to a predetermined value for a predetermined time period beginning after a start of the receiver ON time interval.

8. The combination of claim 1, wherein the differential integrator has an adjustable integrator gain, and wherein the control circuit generates an integrator gain control signal for setting the adjustable integrator gain to a first value for a first predetermined period of time beginning after a start of the receiver ON time interval, and for setting the adjustable integrator gain to a second value lower than the first value for a remainder of the receiver ON time interval.

9. The combination of claim 1, wherein the differential integrator has an adjustable integrator gain, and wherein the control circuit generates an integrator gain control signal for setting the adjustable integrator gain to a first value for a first predetermined period of time beginning at a start of the receiver ON time interval, and for setting the adjustable integrator gain to a second value lower than the first value for a remainder of the receiver ON time interval.

10. The combination of claim 1, and further comprising a demodulator coupled to the output of the second amplifier for demodulating the second differential amplified signal.

11. A selective call receiver comprising the combination of claim 10.

12. In combination, a receiver circuit for receiving a signal detected by an antenna, and a control circuit for controlling ON and OFF time of the receiver circuit, the receiver circuit comprising:

a radio frequency (RF) amplifier coupled to the antenna for amplifying the signal detected by the antenna and generating an amplified signal;

a mixer coupled to the RF amplifier for mixing the amplified signal with an oscillator signal of a predetermined frequency and generating at an output a mixed signal;

an amplifier stage coupled to the mixer comprising;

an amplifier coupled to the output of the mixer for amplifying the mixed signal and generating at an output a differential amplified signal;

a differential integrator coupled to the output of the amplifier for receiving as input the differential amplified signal and generating at an output a differential integrator output; and

a summing network coupled to the output of the differential integrator and to the output of the amplifier, the summing network summing the differential integrator output with the differential amplified signal for canceling any DC offsets of the amplifier;

wherein the control circuit generates a receiver power control signal comprising a receiver ON time interval for turning ON the RF amplifier, mixer and amplifier stage, and a receiver OFF time interval for turning OFF the RF amplifier, mixer and amplifier stage.

13. The combination of claim 12, wherein the amplifier of the amplifier stage is a transconductance amplifier.

14. The combination of claim 12, wherein the differential integrator comprises an integrator reset, and wherein the control circuit generates an integrator reset control signal for resetting the differential integrator beginning a predetermined time period prior to an end of the receiver OFF time interval, and ending at a beginning of the receiver ON time interval.

15. The combination of claim 12, wherein the differential integrator comprises an integrator reset, and wherein the control circuit generates an integrator reset control signal for resetting the differential integrator for a predetermined time period beginning at the receiver ON time interval.

16. The combination of claim 12, wherein the differential integrator comprises an integrator reset, and wherein the control circuit generates an integrator reset control signal for resetting the differential integrator for a predetermined time period beginning prior to an end of the receiver OFF time interval, and ending a predetermined time period after a beginning of the receiver ON time interval.

17. The combination of claim 12, wherein the differential integrator has an adjustable integrator gain, and wherein the control circuit generates an integrator gain control signal for setting the adjustable integrator gain to a predetermined value for a predetermined time period beginning after a start of the receiver ON time interval.

18. The combination of claim 12, wherein the differential integrator has an adjustable integrator gain, and wherein the control circuit generates an integrator gain control signal for setting the adjustable integrator gain to a first value for a first predetermined period of time beginning after a start of the receiver ON time interval, and for setting the adjustable integrator gain to a second value lower than the first value for a remainder of the receiver ON time interval.

19. The combination of claim 12, wherein the differential integrator has an adjustable integrator gain, and wherein the control circuit generates an integrator gain control signal for setting the adjustable integrator gain to a first value for a first predetermined period of time beginning at a start of the receiver ON time interval, and for setting the adjustable integrator gain to a second value lower than the first value for a remainder of the receiver ON time interval.

20. The combination of claim 12, and further comprising a demodulator coupled to the output of the amplifier for demodulating the differential amplified signal.

21. A selective call receiver comprising the combination of claim 20.