Method for fabricating MOS device with reduced anti-punchthrough region

• US 5,472,897 A
• Filed: 01/10/1995
• Issued: 12/05/1995
• Est. Priority Date: 01/10/1995
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hong, Gary, Hsu, Chen-Chung
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US08/370,611
• Time in Patent Office: 329 Days
• Field of Search: 437/41, 437/44, 437/45, 437/162, 257/336, 257/344, 257/402
• US Class Current: 438/291
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method of fabricating MOS device with anti-punchthrough region is described. The area of anti-punchthrough region is reduced by using the control of double spacers. Moreover, this method utilizes the buried contact structure to connect to the source/drain regions, which not only reduces the contact resistance but also reduces the device size since the metal contact can be provided over the field oxide layer instead of the source/drain regions. Hence, this method is capable of fabricating submicron devices for semiconductor integrated circuit.

Claims

1. A method for fabricating MOS device, comprising the steps of:

providing a semiconductor substrate of a first conductivity type which has a device isolation layer formed thereon;

sequentially forming a first conducting layer and a barrier layer on said semiconductor substrate;

patterning said barrier layer to form an opening;

forming first sidewall spacers on the sidewalls of said barrier layer;

etching a portion of said first conducting layer not covered by said barrier layer and said first sidewall spacer to expose an area of said semiconductor substrate which will subsequently define a gate region;

forming second sidewall spacers on sidewalls of said first sidewall spacers and on said first conducting layer;

implanting impurities of the first conductivity type through an opening defined between said second sidewall spacers and into said semiconductor substrate to form an anti-punchthrough region therein;

forming a gate oxide layer on the surface of said semiconductor substrate between said second sidewall spacers;

forming a second conducting layer overlying said barrier layer, said first sidewall spacer, said second sidewall spacer, and said gate oxide layer;

etching a portion of said second conducting layer over said barrier layer, whereby the remaining portion of said second conducting layer within said opening forms a gate;

removing said barrier layer;

implanting impurities of a second conductivity type into said first conducting layer and said gate, wherein said impurities of the second conductivity type diffuse into said semiconductor substrate to form both heavily doped source/drain regions under said first conducting layer and lightly doped source/drain regions under said second sidewall spacers simultaneously;

forming a dielectric layer overlying the whole surface of said semiconductor substrate; and

forming metal contacts in said dielectric layer.

2. The method of claim 1, wherein said first conducting layer is a polysilicon layer.

3. The method of claim 1, wherein said barrier layer is a silicon nitride layer.

4. The method of claim 1, wherein said first and second sidewall spacers comprise silicon dioxide.

5. The method of claim 1, wherein said impurities of the first conductivity type are boron ions with an implantation energy of about 150 KeV and a dosage of about 1×

10¹² atoms/cm².

6. The method of claim 1, wherein said gate oxide layer has a thickness of between 50 Å

to 100 Å

.

7. The method of claim 1, wherein said second conducting layer is a polysilicon layer.

8. The method of claim 1, wherein said impurities of the second conductivity type are arsenic ions with an implantation energy of about 80 KeV and a dosage of between 1×

10¹⁵ to 8×

10¹⁵ atoms/cm².

9. The method of claim 1, wherein said dielectric layer is made of a material selected from the group consisting of silicon dioxide, polyimide, and borophosphosilicate glass.

10. The method of claim 1, wherein said metal contacts are formed in positions of said dielectric layer above said heavily doped source/drain regions.

11. The method of claim 1, wherein said metal contacts are formed in positions of said dielectric layer above said device isolation layer.

12. The method of claim 1, wherein after patterning said first conducting layer a metal silicide layer is formed on said first conducting layer and said gate.

13. The method of claim 12, wherein said metal silicide layer is a titanium silicide layer.