Wafer joined optoelectronic integrated circuits and method

• US 5,472,914 A
• Filed: 07/14/1994
• Issued: 12/05/1995
• Est. Priority Date: 07/14/1994
• Status: Expired due to Fees

• Current Assignee: The United States of America As Represented By The Secretary of Agriculture
• Original Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Inventors: Davis, Andrew, Vaccaro, Kenneth, Lorenzo, Joseph P., Martin, Eric A.
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/274,882
• Time in Patent Office: 509 Days
• Field of Search: 437/2, 437/3, 437/6, 437/209, 437/974, 148/DIG. 135, 257/449, 257/460, 257/461, 257/462, 257/466
• US Class Current: 438/59
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/1446 in a repetitive configuration
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/135 Removal of substrate

Abstract

A full wafer to full wafer integrated circuit fabrication process wherein substrate removal and replacement of one wafer is used to enable an accurate alignment of this wafer with features of a receiving wafer during a see through alignment step. The invention is disclosed in terms of a wafer of photo field effect transistors being combined with a wafer of circuit devices that attend the photo field effect transistor devices. Use of the invention with the different material combination option desired for a photodetector device and its attending circuitry is also disclosed. Advantages over the more conventional chip by chip combination of wafer devices are also disclosed.

Claims

1. The full wafer method of fabricating first semiconductor material comprised and second semiconductor material comprised photo transducer inclusive electronic circuit assemblies comprising the steps of:

forming on an exposed surface of a first semiconductor material first wafer substrate member a buffer and stop etch layer of a first metal inclusive alloy;

growing on said buffer and stop etch layer an optical energy absorbing layer of second semiconductor material composition;

depositing on said second semiconductor material layer a current blocking barrier layer of a second metal inclusive alloy;

removing lateral area portions of said formed, grown and deposited layers to define in the remainder thereof upstanding epitaxial layered mesas of said second semiconductor material included composition;

disposing layers of ohmic electrical contact first metal alloy on selected contact areas of said upstanding epitaxial layered mesas;

fabricating electrical gate non-conductive electrodes of second metal alloy composition on selected areas of said upstanding epitaxial layered mesas;

attaching exposed mesa surface portions of said wafer of photodetector devices to a surface coated optically transparent intermediary second substrate member;

removing said first semiconductor material first wafer from said second intermediary substrate member attached mesas to expose said optical energy layer backside surface portion of each said mesa;

visually aligning said second intermediary substrate member fixed wafer array of mesas and said disposed and fabricated areas of first and second metal alloy attendant thereto with registered and additional metal attended electrical circuit areas of a third substrate member second semiconductor wafer;

contacting and bonding together said second substrate member metal alloy and said third substrate member additional metal to form an array of two-wafer received electrical circuit assemblies having an exposed backside photodetector input port each;

removing said intermediary second substrate member from said bonded together electrical circuit assemblies; and

segregating said array of two substrate wafer received electrical circuit assemblies into individual circuit die of said second semiconductor and said second substrate member respective dispositions and exposed backside photodetector input port each.

2. The method of claim 1 wherein:

said wafer of first semiconductor material is comprised of indium phosphide;

said buffer and stop etch layer of metal inclusive alloy is comprised of indium aluminum arsenide;

said optical energy absorbing layer of second semiconductor material is comprised of indium gallium arsenide;

said current blocking barrier layer is comprised of indium aluminum arsenide;

said ohmic electrical contact first metal alloy is comprised of gold germanium nickel; and

said electrical gate non conductive electrode second metal alloy is comprised of titanium gold.

3. The method of claim 2 wherein said growing of an optical energy absorbing layer includes a molecular beam epitaxy growth process.

4. The method of claim 2 wherein said deleting step includes a thinning by polishing first step and a removing by etching second step.

5. The method of claim 1 further including the step of covering said upstanding mesas and said metal alloy contact and electrode members thereon with a passivation coating of silicon dioxide.

6. The method of claim 2 wherein said removing step includes removal of said deposited grown and formed layers of indium aluminum arsenide, indium gallium arsenide, and indium aluminum arsenide down to said indium phosphide wafer surface in regions intermediate said ohmic electrical contact metal.

7. The method of claim 1 wherein disconnecting step includes etching away of an oxide undercut layer.

8. The method of claim 1 wherein said visually aligning step includes viewing said third substrate member registered additional metal attended electrical circuit areas through said first semiconductor material first wafer removed mesa structure in a contact mask aligner apparatus.

9. The method of claim 1 wherein said attaching step includes attachment via an electrically insulating thermally conductive transparent epoxy adhesive to said second substrate member.

10. The method of claim 1 wherein said contacting and bonding step includes a thermal anneal bonding step.

11. The method of claim 1 wherein said disconnecting step includes selective undercut etching of a surface coating layer portion of said intermediary second substrate member.

12. The method of fabricating dissimilar wafer received photo field effect transistor electrical circuit assemblies comprising the steps of:

fabricating an array of epitaxial layered first semiconductor material comprised, mesa member configured, photo field effect transistor elements that are received via metal conductor bearing mesa plateau surfaces thereof on a secondary substrate wafer member;

visually aligning said mesa members and said mesa connected metal conductors with congruently complementary metal conductors of a tertiary permanent substrate wafer member;

contacting and bonding together said metal conductors of said secondary and tertiary wafer substrate members to form an array of two-wafer received phototransistor assemblies;

removing said secondary substrate wafer member from said array of phototransistor assemblies;

segregating said array of phototransistor assemblies into sub assemblies of at least one phototransistors each.

13. The method of claim 12 further including the step of fabricating on said tertiary substrate member prior to said visually aligning step an array of photo field effect transistor complementing electrical signal operated electrical circuits.

14. The method of claim 13 wherein said secondary and tertiary substrate wafer members are comprised of different and process-incompatible semiconductor materials.

15. The method of claim 12 further including the step of forming said mesa configured first semiconductor material comprised epitaxial layers in epitaxial relationship with a different semiconductor material primary substrate member.

16. The method of claim 15 wherein said mesa configured epitaxial layers are comprised of arsenic inclusive semiconductor material and said primary substrate member is comprised of phosphorous inclusive semiconductor material.