Thin film transistor

• US 5,473,168 A
• Filed: 04/26/1994
• Issued: 12/05/1995
• Est. Priority Date: 04/30/1993
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Katayama, Mikio, Kawai, Katsuhiro
• Primary Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US08/233,805
• Time in Patent Office: 588 Days
• Field of Search: 257/61, 257/66, 257/64, 257/347, 257/365, 257/72, 257/62, 257/63
• US Class Current: 257/61
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate

Abstract

The thin film transistor of the invention includes a substrate; a gate electrode formed on the substrate; a semiconductor layer insulated from the gate electrode, the semiconductor layer being formed on the substrate to cover the gate electrode; a first contact layer and a second contact layer which are made of n-type microcrystalline silicon having a resistivity of 10 Ωcm or less, the first and second contact layers being in contact with the semiconductor layer so as cover part of the gate electrode; a source electrode which is in contact with part of the first contact layer; and a drain electrode which is in contact with part of the second contact layer.

Claims

1. A thin film transistor comprising:

a substrate;

a gate electrode formed on said substrate;

a semiconductor layer insulated from said gate electrode, said semiconductor layer being formed above said substrate to cover said gate electrode;

a first contact layer and a second contact layer which are made of n-type microcrystalline silicon having a resistivity of 10 Ω

cm of less, each of said first and second contact layers having a top surface and a bottom surface, one of the top surface and the bottom surface being in contact with said semiconductor layer to cover part of said gate electrode, an outer edge of each of the first and second contact layers being in alignment with an outer edge of the semiconductor layer;

a source electrode which is in contact with part of the other of the top surface and the bottom surface of said first contact layer; and

a drain electrode which is in contact with part of the other of the top surface and the bottom surface of said second contact layer,

wherein at least one of said source and drain electrodes is disposed not to overlap said gate electrode,

wherein a width in a channel width direction of at least one of said source and drain electrodes is smaller than a width in the channel width direction of said first and second contact layers, and

wherein said width in the channel width direction of said at least one of said source and drain electrodes is determined so that an end of said at least one of said source and drain electrodes is located apart from an end of a corresponding one of said first and second contact layers by a distance of 3 μ

m or more.

2. A thin film transistor comprising:

a substrate;

a gate electrode formed on said substrate;

a semiconductor layer insulated from said gate electrode, said semiconductor layer being formed above said substrate to cover said gate electrode;

a first contact layer and a second contact layer which are made of n-type microcrystalline silicon having a resistivity of 10 Ω

cm of less, each of said first and second contact layers having a top surface and a bottom surface, one of the top surface and the bottom surface being in contact with said semiconductor layer to cover part of said gate electrode, an outer edge of each of the first and second contact layers being in alignment with an outer edge of the semiconductor layer;

a source electrode which is in contact with part of the other of the top surface and the bottom surface of said first contact layer; and

a drain electrode which is in contact with part of the other of the top surface and the bottom surface of said second contact layer,

wherein at least one of said source and drain electrodes is disposed not to overlap said gate electrode,

wherein a width in a channel width direction of at least one of said source and drain electrodes is smaller than a width in the channel width direction of said first and second contact layers, and

wherein said source electrode and said drain electrode are formed at positions displaced from each other in the channel width direction.

3. A thin film transistor comprising:

a substrate;

a gate electrode formed on said substrate;

a semiconductor layer insulated from said gate electrode, said semiconductor layer being formed above said substrate to cover said gate electrode;

a first contact layer and a second contact layer which are made of n-type microcrystalline silicon having a resistivity of 10 Ω

cm of less, each of said first and second contact layers having a top surface and a bottom surface, one of the top surface and the bottom surface being in contact with said semiconductor layer to cover part of said gate electrode, an outer edge of each of the first and second contact layers being in alignment with an outer edge of the semiconductor layer;

a source electrode which is in contact with part of the other of the top surface and the bottom surface of said first contact layer; and

a drain electrode which is in contact with part of the other of the top surface and the bottom surface of said second contact layer,

wherein at least one of said source and drain electrodes is disposed not to overlap said gate electrode,

wherein a width in a channel width direction of at least one of said source and drain electrodes is smaller than a width in the channel width direction of said first and second contact layers, and

wherein said gate electrode includes a first portion and a second portion directly under the semiconductor layer, said first portion having a first width in a channel length direction, and said second portion having a second width in the channel length direction which is smaller than said first width.

4. A thin film transistor comprising:

a substrate;

a source electrode and a drain electrode both formed on said substrate;

a first contact layer and a second contact layer which are made of n-type microcrystalline silicon having a resistivity of 10 Ω

cm or less, said first contact layer being in contact with part of said source electrode, and said second contact layer being in contact with part of said drain electrode;

a semiconductor layer which is in contact with said first and second contact layers, an outer edge of the semiconductor layer being in alignment with an outer edge of each of the first and second contact layers; and

a gate electrode insulated from said semiconductor layer, said gate electrode covering part of said first contact layer and part of said contact layer;

wherein said width in the channel width direction of said at least one of said source and drain electrodes is determined so that an end of said at least one of said source and drain electrodes is located apart from an end of a corresponding one of said first and second contact layers by a distance of 3 μ

m or more;

wherein said source electrode and said drain electrode are formed at positions displaced from each other in the channel width direction; and

wherein said semiconductor layer is formed directly on said substrate, said first and second contact layers are formed directly on said semiconductor layer, and said source electrode and said drain electrode are formed to cover part of said first contact layer and part of said second contact layer, respectively.

5. A thin film transistor comprising:

a substrate,

a gate electrode formed on said substrate;

a semiconductor layer insulated from said gate electrode, said semiconductor layer being formed above said substrate to cover said gate electrode;

a first contact layer and a second contact layer which are made of n-type microcrystalline silicon having a resistivity of 10 Ω

om or less, each of said first and second contact layers having a top surface and a bottom surface, one of the top surface and the bottom surface being in contact with said semiconductor layer to cover part of said gate electrode, an outer edge of each of the first and second contact layers being in alignment with an outer edge of the semiconductor layer;

a source electrode which is in contact with part of the other of the top surface and the bottom surface of said first contact layer; and

a drain electrode which is in contact with part of the other of the top surface and the bottom surface of said second contact layer,

wherein a width in a channel width direction of at least one of said source and drain electrodes is smaller than a width in the channel width direction of said first and second contact layers,

said gate electrode includes a first portion and a second portion under the semiconductor layer, said first portion having a first width in a channel length direction, and said second portion having a second width in the channel length direction which is smaller than said first width,

wherein said source electrode and said drain electrode cover part of said first portion of said gate electrode.

6. A thin film transistor comprising:

a substrate;

a gate electrode formed on said substrate;

a semiconductor layer insulated from said gate electrode, said semiconductor layer being formed above said substrate to cover said gate electrode;

a first contact layer and a second contact layer which are made of n-type microcrystalline silicon having a resistivity of 10 Ω

cm or less, each of said first and second contact layers having a top surface and a bottom surface, one of the top surface and the bottom surface being in contact with said semiconductor layer to cover part of said gate electrode, an outer edge of each of the first and second contact layers being in alignment with an outer edge of the semiconductor layer;

a source electrode which is in contact with part of the other of the top surface and the bottom surface of said first contact layer;

a drain electrode which is in contact with part of the other of the top surface and the bottom surface of said second contact layer,

wherein said source electrode covers part of said first contact layer, and said drain electrode covers part of said second contact layer, and

wherein each of said source and drain electrodes includes a first portion and a second portion, said first portion having a first width in a channel width direction, said second portion having a second width in the channel width direction which is larger than said first width, and wherein said first portion partially covers said gate electrode.