Vertical insulated gate transistor and method of manufacture

• US 5,473,176 A
• Filed: 08/31/1994
• Issued: 12/05/1995
• Est. Priority Date: 09/01/1993
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kakumoto, Munenari
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/296,913
• Time in Patent Office: 461 Days
• Field of Search: 257/284, 257/330, 257/333, 257/192, 257/263, 257/341, 257/622, 437/40, 437/203, 437/107, 437/126, 437/133, 437/228, 437/913
• US Class Current: 257/192
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A vertical insulated gate transistor such as a UMOSFET is manufactured. A source region of first conductivity type is formed on the bottom surface of a substrate. A base region of second conductivity type is formed on the source region. A low-impurity-concentration drift region is formed on the base region. On the top surface of this multilayer structure, a truncated U groove is formed. A buried gate electrode is formed inside the truncated U groove. This structure is effective to reduce gate-drain capacitance Cgd, gate-source capacitance Cgs, and drain resistance r_d, thereby realizing a high-frequency high-output device. A distance between the gate and the drain is determined in a self-aligning manner, so that a fine structure and a high-frequency operation are easily realized and production yield is improved.

Claims

1. A vertical insulated gate transistor having a source electrode on its bottom surface comprising:

a high-impurity-concentration first semiconductor region of first conductivity type serving as a source region;

a second semiconductor region of second conductivity type formed on said first semiconductor region;

a low-impurity-concentration third semiconductor region formed on said second semiconductor region;

a truncated U groove formed from the top surface of said third semiconductor region and substantially reaching to said first semiconductor region;

a high-impurity-concentration fourth semiconductor region of first conductivity type serving as a drain region formed on the top surface of said third semiconductor region along each side of said truncated U groove;

material disposed on the bottom and sidewall of said truncated U groove having a wider band gap than said second semiconductor region; and

a buried gate electrode having a vertical sidewall, buried in said material having a wider band gap,

wherein the upper part of said truncated U groove has sidewalls that are oblique with respect to horizontal surface plane of said third semiconductor region and the lower part of said truncated U groove has sidewalls that are substantially vertical and facing to said second semiconductor region so that the width of an opening of said upper part of said truncated U groove on the top surface of said third semiconductor region is greater than the width of said lower part of said truncated U groove in the vicinity of an interface between said second semiconductor region and said third semiconductor region, and the lateral thickness of said material is thicker in the vicinity of the top surface of said third semiconductor region than that in the vicinity of the interface between said third semiconductor region and said second semiconductor region, and

a distance between the bottom of said buried gate electrode and the bottom of the truncated U groove below said buried gate electrode is larger than a distance between said vertical sidewall of said buried gate electrode and said second semiconductor region.

2. A vertical insulated gate transistor as claimed in claim 1, wherein said material is an insulator.

3. A vertical insulated gate transistor as claimed in claim 2, wherein said insulator is an oxide.

4. A vertical insulated gate transistor as claimed in claim 1 or 2, further comprising:

a low-impurity-concentration fifth semiconductor region of first conductivity type formed between said first semiconductor region and said second semiconductor region.

5. A vertical insulated gate transistor as claimed in claim 1 or 2, further comprising:

a sixth semiconductor region having a narrower band gap than said second semiconductor region, formed between said second and third semiconductor regions.

6. A vertical insulated gate transistor as claimed in claim 1 or 2, wherein said first semiconductor region is an epitaxial film grown on a high-impurity-concentration substrate of first conductivity type.

7. A vertical insulated gate transistor as claimed in claim 1 or 2, wherein said fourth semiconductor region has a narrower band gap than said third semiconductor region.

8. A method of manufacturing a vertical insulated gate transistor, comprising the steps of:

(1) continuously epitaxially growing a first semiconductor region of first conductivity type having a high-impurity-concentration, a second semiconductor region of second conductivity type, and a third semiconductor region having a low-Impurity-concentration on a substrate of first conductivity type having a high-impurity concentration serving as a source region, and forming a truncated U groove from the top surface of the third semiconductor region to reach the first semiconductor region;

(2) disposing a wide band gap material having a wider band gap than the second semiconductor region on the bottom and sidewall of the truncated U groove, and

burying high conductive material in the wide band gap material to form a buried gate electrode; and

(3) forming a high-impurity-concentration fourth semiconductor region of first conductivity type serving as a drain region on the top surface of the third semiconductor region in a self-aligning manner employing said wide band gap material as a mask.

9. A method of manufacturing a vertical insulated gate transistor as claimed in claim 8, wherein the truncated U groove is formed in said step (1) by:

forming a V-shaped groove serving as an upper part of said truncated U groove on the top surface of the third semiconductor region;

filling the V-shaped groove with said wide band gap material; and

etching said wide band gap material to form a trench in the center of said V-shaped groove, and further etching the semiconductor regions downward to the first semiconductor region to form a U groove serving as a lower part of said truncated U groove.

10. A method of manufacturing a vertical insulated gate transistor as claimed in claim 8, wherein the fourth semiconductor region is formed in said step (3) by a selective epitaxial growth in the window part of said wide band gap material serving as a mask.

11. A method of manufacturing a vertical insulated gate transistor as claimed in claim 8, wherein said wide band gap material disposed on the bottom of the truncated U groove in said step (2) is an oxide film formed by implanted oxygen ions, and a gate oxide film on the sidewall of the truncated U groove is formed by thermal oxidization.

12. A method of manufacturing a vertical insulated gate transistor, comprising the steps of:

(1) continuously epitaxially growing a high-impurity-concentration first semiconductor region of first conductivity type, a second semiconductor region of second conductivity type, and a low-impurity-concentration third semiconductor region on a high-impurity-concentration substrate of first conductivity type serving as a source region, forming a V-shaped groove on the top surface of the third semiconductor region, filling the V-shaped groove with wide band gap material having a wider band gap than the second semiconductor region, and forming a U groove at the center of the V-shaped groove downward to the first semiconductor region, to thereby form a truncated U groove;

(2) forming an oxidization resistive film only on the sidewall of the U groove, selectively oxidizing the bottom of the U groove with use of the oxidization resistive film, to form a thick oxide film only on the bottom of the U groove, removing the oxidization resistive film, forming a gate oxide film on the sidewall of the U groove, and filling the U groove with highly conductive material serving as a gate electrode; and

(3) employing said wide band gap material as a mask and forming a high-impurity-concentration fourth semiconductor region of first conductivity type serving as a drain region on the top surface of the third semiconductor region in a self-aligning manner.