Semiconductor memory cell for holding data with small power consumption

• US 5,473,178 A
• Filed: 04/05/1994
• Issued: 12/05/1995
• Est. Priority Date: 11/26/1990
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Konishi, Yasuhiro
• Primary Examiner(s): JACKSON JR, JEROME
• Application Number:
  US08/223,187
• Time in Patent Office: 609 Days
• Field of Search: 257/297, 257/301, 307/499, 307/501, 365/149, 365/186
• US Class Current: 257/297
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

A DRAM includes an N-type well formed on a main surface of a P-type semiconductor substrate, an N-type impurity region formed on the main surface of the P-type semiconductor substrate, a P-type impurity region formed in the N-type well to be a storage node of a memory capacitor, and a polycrystalline silicon layer for connecting the P-type impurity region and the N-type impurity region. The N-type impurity layer, the P-type impurity layer, and the polycrystalline silicon layer constitute the storage node of the memory capacitor, and electrons of minority carriers flowing from the substrate to the N-type impurity layer are recombined with holes flowing from the N-type well to the P-type impurity layer.

Claims

1. A DRAM comprising:

a semiconductor substrate of a first conductivity type having a main surface;

a first region of a second conductivity type formed on the main surface of said semiconductor substrate;

a planar capacitor formed on said main surface;

a second region of a second conductivity type formed on said main surface;

a third region of the first conductivity type formed in said first region of the second conductivity type and on the main surface of said semiconductor substrate; and

a first conductive layer connecting said third region of the first conductivity type and said second region of the second conductivity type to recombine first minority carriers flowing from said semiconductor substrate to said second region of the second conductivity with second minority carriers flowing from said first region of the second conductivity type to said third region of the first conductivity type;

wherein

said third region of the first conductivity type, said second region of the second conductivity type, and said first conductive layer constitute a storage node connecting to the planar capacitor.

2. The DRAM according to claim 1, wherein said first region of the second conductivity type and said third region of the first conductivity type are biased reversely to each other.

3. The DRAM according to claim 1, wherein said third region of the first conductivity type and said second region of the second conductivity type are separated by an oxide film formed on said main surface.

4. The DRAM according to claim 1, wherein a junction part of said third region of the first conductivity type and said first region of the second conductivity type has a first area.

5. A DRAM comprising:

a semiconductor substrate of a first conductivity type having a main surface; and

a storage node formed on said main surface including

an impurity region of a second conductivity type formed on said main surface of said semiconductor substrate; and

compensating means formed on said main surface of said semiconductor substrate for compensating the fluctuations in the potential of said impurity region of second conductivity type caused by minority carriers flowing from said semiconductor substrate to said impurity region, said storage node being connected to a stacked capacitor,

wherein said compensating means includes;

a first region of the second conductivity type formed on said main surface of said semiconductor substrate;

a second region of the first conductivity type formed in said first region of said second conductivity type and on said main surface of said semiconductor substrate; and

a conductive layer for connecting said second region of the first conductivity type and said impurity region of the second conductivity type.

6. The DRAM according to claim 5, wherein

said semiconductor substrate is kept at a first potential, and

said first region of the second conductivity type is kept at a second potential.

7. The DRAM according to claim 6, wherein said substrate of the first conductivity type and said impurity region of the second conductivity type are kept biased reversely to each other, and said first region of the second conductivity type and said second region of the first conductivity type are kept biased reversely to each other.

9. The DRAM according to claim 5, wherein said impurity region is formed in contact with said substrate.

10. The DRAM according to claim 5, wherein said impurity region is buried in said substrate.

8. A DRAM memory cell circuit comprising:

a transistor having one end connected to a bit line and the other end connected through a storage node to a first electrode of a trench capacitor and operating in response to a predetermined potential, said storage node comprising first and second regions of opposite conductivity type and a conductive layer connecting said first and second regions;

a first diode having one end connected to a first electrode of said capacitor and the other end connected to a negative potential; and

a second diode having one end connected to said first electrode of said capacitor and the other end connected to a positive potential.