Semiconductor device with an MOST provided with an extended drain region for high voltages

• US 5,473,180 A
• Filed: 07/11/1994
• Issued: 12/05/1995
• Est. Priority Date: 07/12/1993
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Ludikhuize, Adrianus W.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/273,527
• Time in Patent Office: 512 Days
• Field of Search: 257/336, 257/339, 257/408, 257/404, 257/653, 257/344, 257/345, 257/367
• US Class Current: 257/336
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device with a semiconductor body (1) includes a surface region (3) of a first conductivity type which adjoins a surface and in which a field effect transistor is provided which includes a channel region (7) with a gate electrode (8) above it, and a source region (4), a drain region (5) and a drain extension region (6). The drain extension region (6) serves to improve the drain breakdown voltage of the field effect transistor. In practice, a high breakdown voltage is accompanied by a comparatively high on-resistance of the transistor. According to the invention, the drain extension region (6) has a geometry different from that in known transistors, i.e. the drain extension region (6) includes a number of zones (25) of the second conductivity type which extend from the channel region (7) to the drain region (5) and which have a width (26) and doping concentration such that, when the voltage difference across the blocked pn junction (28) between the surface region (3) and the drain extension region (6) is increased, the drain extension region (6) is fully depleted at least locally before drain breakdown occurs. This renders it possible to choose the number and the width (26) of the zones (25) as an additional parameter of the device. Such devices have comparatively high drain breakdown voltages and comparatively low on-resistances which cannot be realized with a continuous drain extension region (6).

Claims

1. A semiconductor device with a semiconductor body comprising a surface region of a first conductivity type which adjoins a surface and in which a field effect transistor with an insulated gate is provided, with source and drain regions of the second, opposed conductivity type in the surface region and a drain extension region of the second conductivity type which adjoins the drain region and the surface, which has a lower doping concentration than the drain region, and which extends longitudinally in the direction of the source region, with a channel region of the first conductivity type situated between the drain extension region and the source region, and with a gate electrode situated above the channel region and separated from the channel region by an insulating layer, characterized in that the drain extension region comprises a plurality of zones of the second conductivity type, said zones extending from the channel region to the drain region and having means for fully depleting the drain extension region and comprising said zones having a width and doping concentration such that upon an increase in the voltage difference across the blocked pn junction between the surface region and the drain extension region the drain extension region is fully depleted at least locally before drain breakdown takes place, said zones being spaced apart at said channel region.

2. A semiconductor device as claimed in claim 1, characterized in that the width of the zones is approximately equal to the depth of the drain extension region, while the doping concentration decreases from the centre of each zone to an edge of the zone.

3. A semiconductor device as claimed in claim 1, characterized in that the width of the zones increases from the channel region to the drain region.

4. A semiconductor device as claimed in claim 1, characterized in that the zones are interconnected by a region of the second conductivity type in a portion of the drain extension region which adjoins the drain region.

5. A semiconductor device as claimed in claim 1, characterized in that the quantity of dopant atoms in the zones is approximately 6×

10¹² atoms/cm².