Programmable logic device having fast programmable logic array blocks and a central global interconnect array

• US 5,473,266 A
• Filed: 10/18/1994
• Issued: 12/05/1995
• Est. Priority Date: 04/19/1993
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Li, Ken-Ming, Leong, William, Kiani, Khusrow, Ahanin, Bahram, Balicki, Janusz K., Nouban, Bezhad
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): DRISCOLL, BENJAMIN
• Application Number:
  US08/324,860
• Time in Patent Office: 413 Days
• Field of Search: 307/465, 307/465.1, 340/825.83, 340/825.84, 340/825.85, 340/825.86, 340/825.87, 326/39, 326/40, 326/41
• US Class Current: 326/41
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence

Abstract

A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

Claims

1. A programmable logic device comprising:

a plurality of first logic signal conductors disposed in an array located primarily in a central region on the programmable logic device;

a plurality of global control input conductors disposed in the central region, and being distinct from the first logic signal conductors; and

a plurality of programmable logic array blocks disposed on both sides of the central region, each programmable logic array block comprising;

a plurality of second logic signal conductors,

a first array of programmable switches for connecting the first logic signal conductors to the second logic signal conductors, wherein the first array of programmable switches provides at least two ways in which each of the first logic signal, conductors may be connected to one of the plurality second logic signal conductors,

a plurality of local control input conductors for transmitting control signals to logic devices in the programmable logic array block, and

a programmable configuration array for programmably connecting any of the second logic signal conductors and the global control input conductors to the local control input conductors.

2. A programmable logic device as described in claim 1 further comprising a programmable memory means embedded in the programmable logic device beneath the first logic signal conductors, the programmable memory means for programmably connecting the conductors in the programmable logic device.

3. A programmable logic device as described in claim 2 wherein the programmable memory means comprises an electrically-erasable programmable read-only memory.

4. A programmable logic device as described in claim 1 wherein each programmable logic array block further comprises:

a plurality of local feedback conductors;

a second array of switches for connecting any of the global control input conductors, the second logic signal conductors, and the local feedback conductors to any of the local control input conductors;

a plurality of macrocell input conductors;

a third array of switches for connecting any of the second logic signal conductors and the local feedback conductors to any of the macrocell input conductors;

a plurality of programmable macrocells capable of performing multi-variable logic functions, the programmable macrocells comprising;

a plurality of logic signal input terminals connected to the macrocell input conductors,

a plurality of control signal input terminals connected to the local control input conductors,

an allocation input terminal,

an allocation output terminal, and

a first macrocell output terminal connected to one of the local feedback conductors and one of the first logic signal conductors;

a plurality of allocation signal conductors, each of the allocation signal conductors being connected between the allocation output terminal of one of the programmable macrocells and the allocation input terminal of an adjacent programmable macrocell; and

a plurality of buffer/driver circuits in series with the local control input conductors, the local feedback conductors, and the second logic signal conductors.

5. A programmable logic device as described in claim 4 wherein the first, second, and third arrays of switches comprise multiplexers, the multiplexers being controlled by static random-access memory cells embedded in the programmable logic array block.

6. A programmable logic device as described in claim 1 wherein each programmable logic array block further comprises:

a first array of switches for connecting the first logic signal conductors to the second logic signal conductors;

a plurality of local feedback conductors;

a second array of switches for connecting any of the global control input conductors, the second logic signal conductors, and the local feedback conductors to any of the local control input conductors;

a plurality of macrocell input conductors;

a third array of switches for connecting any of the second logic signal conductors and the local feedback conductors to any of the macrocell input conductors;

a plurality of first expander conductors;

a plurality of second expander conductors;

a fourth array of switches for connecting any of the first expander conductors to any of the second expander conductors;

a plurality of programmable macrocells capable of performing multi-variable logic functions, each of the programmable macrocells comprising;

a plurality of logic signal input terminals connected to selected macrocell input conductors,

a macrocell expander input terminal connected to one of the second expander conductors,

a plurality of control signal input terminals connected to the local control input conductors,

an allocation input terminal,

an allocation output terminal, and

a first macrocell output terminal connected to one of the local feedback conductors and one of the first logic signal conductors;

a plurality of combinatorial logic devices, each combinatorial logic device having a plurality of expander inputs and an expander output, the expander inputs being connected to selected macrocell input conductors, and the expander output being connected to one of the first expander conductors;

a plurality of allocation signal conductors, each of the allocation signal conductors being connected between the allocation output terminal of one of the programmable macrocells and the allocation input terminal of an adjacent programmable macrocell; and

a plurality of buffer/drivers in series with the first expander conductors, the local control input conductors, the local feedback conductors, and the second logic signal conductors.

7. A programmable logic device as described in claim 6 wherein the first, second, third, and fourth arrays of switches comprise multiplexers, the multiplexers being controlled by static random-access memory cells embedded in the programmable logic array block.

8. A programmable logic device as described in claim 6 wherein the combinatorial logic devices comprise programmable look-up tables.

9. A programmable logic device comprising:

a plurality of first logic signal conductors disposed in an array located primarily in a central region on the programmable logic device;

a plurality of global control input conductors disposed in the central region, and being distinct from the first logic signal conductors;

a programmable memory means embedded in the programmable logic device beneath the first logic signal conductors; and

a plurality of programmable logic array blocks disposed on both sides of the central region, each programmable logic array block comprising;

a plurality of second logic signal conductors,

a first array of switches for connecting the first logic signal conductors to the second logic signal conductors, wherein the first array of switches provides at least two ways in which each of the first logic signal conductors may be connected to one of the plurality second logic signal conductors,

a plurality of local feedback conductors,

a plurality of local control input conductors,

a second array of switches for connecting any of the global control input conductors, the second logic signal conductors, and the local feedback conductors to any of the local control input conductors,

a plurality of macrocell input conductors,

a third array of switches for connecting any of the second logic signal conductors and the local feedback signal conductors to any of the macrocell input conductors,

a plurality of programmable macrocells capable of performing multi-variable logic functions, the programmable macrocells comprising;

a plurality of logic signal input terminals connected to the macrocell input conductors,

a plurality of control signal input terminals connected to the local control input conductors,

an allocation input terminal,

an allocation output terminal, and

a first macrocell output terminal connected to one of the local feedback conductors and one of the first logic signal conductors,

a plurality of allocation signal conductors, each of the allocation signal conductors being connected between the allocation output terminal of one of the programmable macrocells and the allocation input terminal of an adjacent programmable macrocell, and

a plurality of buffer/driver circuits in series with the local control input conductors, the local feedback conductors, and the second logic signal conductors.

10. A programmable logic device as described in claim 9 wherein the first, second, and third arrays of switches comprise multiplexers, the multiplexers being controlled by static random-access memory cells embedded in the programmable logic array block.

11. A programmable logic device as described in claim 9 wherein the programmable memory means comprises an electrically-erasable programmable read-only memory.

12. A programmable logic device comprising:

a plurality of first logic signal conductors disposed in an array located primarily in a central region on the programmable logic device;

a plurality of global control input conductors disposed in the central region, and being distinct from the first logic signal conductors;

an electrically-erasable programmable read-only-memory embedded in the programmable logic device beneath the first logic signal conductors;

a plurality of programmable logic array blocks disposed on both sides of the central region, each programmable logic array block comprising;

a plurality of second logic signal conductors,

a first array of multiplexers for connecting the first logic signal conductors to the second logic signal conductors, wherein the first array of multiplexers provides at least two ways in which each of the first logic signal conductors may be connected to one of the plurality second logic signal conductors,

a plurality of local feedback conductors,

a plurality of local control input conductors,

a second array of multiplexers for connecting any of the global control input conductors, the second logic signal conductors, and the local feedback conductors to any of the local control input conductors,

a plurality of macrocell input conductors,

a third array of multiplexers for connecting any of the second logic signal conductors and the local feedback conductors to any of the macrocell input conductors,

sixteen programmable macrocells capable of performing multi-variable logic functions, the programmable macrocells comprising;

a plurality of logic signal input terminals connected to the macrocell input conductors,

a plurality of control signal input terminals connected to the local control input conductors,

an allocation input terminal,

an allocation output terminal, and

a first macrocell output terminal connected to one of the local feedback conductors and one of the first logic signal conductors,

a plurality of allocation signal conductors, each of the allocation signal conductors being connected between the allocation output terminal of one of the programmable macrocells and the allocation input terminal of an adjacent programmable macrocell, and

a plurality of buffer/driver circuits in series with the local control input conductors, the local feedback conductors, and the second logic signal conductors; and

a plurality of static random-access memory cells embedded in the programmable logic device for controlling the first, second, and third arrays of multiplexers.