Device for the protection of an integrated circuit against power supply cuts

• US 5,473,496 A
• Filed: 08/02/1993
• Issued: 12/05/1995
• Est. Priority Date: 07/31/1992
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics SA (STMicroelectronics NV)
• Original Assignee: SGS Thomson Microelectronics SA (STMicroelectronics NV)
• Inventors: Rouy, Olivier
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Leja, Ronald W.
• Application Number:
  US08/100,867
• Time in Patent Office: 855 Days
• Field of Search: 361/18, 361/56, 361/58, 361/86, 361/88, 361/92, 361/100, 361/101, 307/360, 307/442, 307/443, 307/465, 307/468, 307/469, 307/473, 307/475, 340/663, 395/750, 395/425, 364/246.6, 364/DIG. 1, 364/273.4, 324/550, 324/537, 324/522, 324/416, 327/74, 326/21, 326/37, 326/44, 326/47, 326/49, 326/56, 326/59, 326/63
• US Class Current: 361/18
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02H 3/24 responsive to undervoltage or no-voltage H02H3/207 takes precedence

Abstract

A circuit for protecting nonvolatile memories against loss of Vcc while Vpp is high. An NMOS gated by Vcc is connected, in series with a load element, between Vpp and ground. The node between the NMOS and the load element gates a PMOS which is interposed between Vpp and the memory. Thus when Vcc fails while Vpp is high, the NMOS will turn off, and the load element will pull up the gate of the PMOS to turn it off, interrupting the Vpp supply. This prevents spurious write or erase operations under these circumstances. The circuit can be designed to trigger at threshold voltages as low as V_TN, and is thus particularly advantageous for operation with specified Vcc values of 3 Volts or less.

Claims

1. A circuit, comprising:

an integrated circuit having connections for a first supply voltage, a second positive supply voltage, and a third positive supply voltage which is higher than said second positive supply voltage;

a load element connected to said third supply voltage;

an N-channel field-effect transistor connected to be controlled by said second supply voltage;

said load element and said N-channel field-effect transistor being operatively connected in series between said first and third supply voltages; and

a P-channel field-effect transistor connected between said third supply voltage and a corresponding one of said connections of said integrated circuit, and connected to be controlled by a node between said load element and said N-channel field-effect transistor;

whereby, when said second supply voltage falls below the threshold voltage of said N-channel field-effect transistor, said N-channel field-effect transistor turns off and ceases to pull down the down the potential of said node, and thereby permits said P-channel field-effect transistor to turn off and disconnect said integrated circuit from said third supply voltage.

2. The circuit of claim 1, wherein said load element consists of a resistor.

3. The circuit of claim 1, wherein said load element has a linear relationship between current and voltage.

4. The circuit of claim 1, further comprising at least one diode-connected transistor connected between said detection node and said load element.

5. The circuit of claim 1, further comprising at least one additional load element connected between said detection node and said first supply voltage.

6. The circuit of claim 1, wherein said load element, said N-channel field-effect transistor, and said P-channel field-effect transistor are provided by discrete components.

7. The circuit of claim 1, wherein one or more of said load element, said N-channel field-effect transistor, and said P-channel field-effect transistor are integrated with said integrated circuit.

8. The circuit of claim 1, wherein said integrated circuit is a non-volatile memory.

9. The circuit of claim 1, wherein said integrated circuit is directly connected to said first and second supply voltages.

10. The circuit of claim 1, wherein said integrated circuit is an EEPROM.

11. A circuit comprising:

circuit element directly connected to receive a first supply voltage and a second supply voltage which is higher than said first supply voltage, and also having a connection for receiving a third supply voltage which is higher than said second supply voltage;

a load element connected between said third supply voltage and a detection node,

an N-channel field-effect transistor connected between said detection node and said first supply voltage, and having a gate operatively connected to be controlled by a voltage which is dependent on said second supply voltage; and

a P-channel field-effect transistor connected between said third supply voltage and said third supply voltage connection of said circuit element, and having a gate operatively connected to said detection node.

12. The circuit of claim 11, wherein said load element consists of a resistor.

13. The circuit of claim 11, further comprising at least one diode-connected transistor connected between said detection node and said load element.

14. The circuit of claim 11, further comprising at least one additional load element connected between said detection node and said first supply voltage.

15. The circuit of claim 11, wherein said load element, said N-channel field-effect transistor, and said P-channel field-effect transistor are provided by discrete components.

16. The circuit of claim 11, wherein one or more of said load element, said N-channel field-effect transistor, and said P-channel field-effect transistor are integrated with said circuit element.

17. The circuit of claim 11, wherein said circuit element is a non-volatile memory.

18. The circuit of claim 11, wherein said circuit element is directly connected to said first and second supply voltages.

19. The circuit of claim 11, wherein said circuit element is an EEPROM.

20. A circuit, comprising:

a circuit element having connections for a first supply voltage, a second positive supply voltage, and a third positive supply voltage which is higher than said second positive supply voltage;

a load element connected to said third supply voltage;

a first switching element connected to be controlled by said second supply voltage;

said load element and said first switching element being operatively connected in series between said first and third supply voltages; and

a second switching element connected between said third supply voltage and a corresponding one of said connections of said circuit element, and connected to be controlled by a node between said load element and said first switching element;

whereby when said second supply voltage fails, said first switching element turns off, and ceases to drive current through said load element, and thereby permits said second switching element to turn off and disconnect said circuit element from said third supply voltage.

21. The circuit of claim 20, wherein said first switching element consists of an N-channel field-effect transistor, and said second switching element consists of a P-channel field-effect transistor.

22. The circuit of claim 20, wherein said load element consists of a resistor.

23. The circuit of claim 20, wherein said load element has a linear relationship between current and voltage.

24. The circuit of claim 20, further comprising at least one diode-connected transistor connected between said node and said load element.

25. The circuit of claim 20, further comprising at least one additional load element connected between said node and said first supply voltage.

26. The circuit of claim 20, wherein said load element, said N-channel field-effect transistor, and said P-channel field-effect transistor are provided by discrete components.

27. The circuit of claim 20, wherein one or more of said load element, said N-channel field-effect transistor, and said P-channel field-effect transistor are integrated with said circuit element.

28. The circuit of claim 20, wherein said circuit element is a non-volatile memory.

29. The circuit of claim 20, wherein said circuit element is directly connected to said first and second supply voltages.

30. The circuit of claim 20, wherein said circuit element is an EEPROM.

31. An integrated circuit, comprising:

connections for receiving a first supply voltage, a second supply voltage which is higher than said first supply voltage, and a third supply voltage which is higher than said second supply voltage;

a circuit block directly connected to receive said first and second supply voltages, and also having a connection for receiving said third supply voltage;

a load element connected between said third supply voltage and a detection node,

an N-channel field-effect transistor connected between said detection node and said first supply voltage, and having a gate operatively connected to be controlled by a voltage which is dependent on said second supply voltage; and

a P-channel field-effect transistor connected between said third supply voltage and said corresponding connection of said circuit block, and having a gate operatively connected to said detection node.

32. The circuit of claim 31, wherein said load element consists of a resistor.

33. The circuit of claim 31, further comprising at least one diode-connected transistor connected between said detection node and said load element.

34. The circuit of claim 31, further comprising at least one additional load element connected between said detection node and said first supply voltage.

35. The circuit of claim 31, wherein said circuit block is an EEPROM memory array, and wherein said third supply voltage provides a Vpp supply thereto.

36. A device for the protection of an integrated circuit against power supply cuts, said device being designed to be supplied with at least one normal supply voltage Vcc and with a programming and/or erasure voltage Vpp, said device comprising

cut-off means inserted in series between the source of the voltage Vpp and the supply input of the integrated circuit corresponding to this source, and

means to activate said cut-off means, connected to the source of the voltage Vcc to activate said cut-off means when the value of the voltage Vcc drops below a certain threshold, said threshold value being determined to activate said cut-off means before said voltage Vcc reaches a value, below which the logic operation of the integrated circuit becomes random.

37. A device according to claim 36, wherein said cut-off means comprises a first P type MOS transistor inserted in series between the source of the voltage Vpp and the corresponding input of the integrated circuit, and a bias resistor connecting the source of the voltage Vpp to the gate of this first transistor, and said means to activate comprises a second N type MOS transistor connected in series between the gate of the first transistor and ground, and means for connecting the gate of this second transistor to the source of the voltage Vcc.

38. A device according to claim 36, wherein the integrated circuit is an electrically erasable and programmable memory.

39. A device according to claim 37, wherein the integrated circuit is an electrically erasable and programmable memory.

40. A method for operating an integrated circuit memory which requires three different supply voltages, comprising the steps of:

providing a load element and a first switching element connected in series between the highest and lowest of said supply voltages, and connecting an intermediate supply voltage to control said first switching element;

and, passing the highest of said supply voltages through a second switch which is connected to automatically turn off whenever said intermediate supply voltage fails and causes said first switching element to interrupt current through said load element, thereby automatically interrupting said highest of said supply voltages at a point before it enters said memory.