Memory architecture and devices, systems and methods utilizing the same
First Claim
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1. A memory comprising:
- a plurality of self-contained memory units for storing data;
a plurality of shift registers, each said shift register including a first parallel data port coupled to a data port of a corresponding one of said self-contained memory units and a serial port;
interconnection circuitry coupled to a second parallel data port of each said shift register; and
control circuitry operable to control the exchange of data between a selected one of said memory units and said interconnection circuitry via said parallel ports of said shift register coupled to said selected memory unit and the exchange of data with said selected one of said memory units through said serial port of said shift register coupled to said selected memory unit.
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Abstract
A memory 200 is provided which includes a plurality of self-contained memory units 201 for storing data. A plurality of shift registers 211 are provided, each including a first parallel port coupled to a data port of a corresponding one of the self-contained memory units 201. Interconnection circuitry 212 is coupled to a parallel data port of each of the shift registers. Control circuitry 208, 213 is provided which is operable to control the exchange of data between a selected one of the memory units and the interconnection circuitry 212 via the shift register 211 coupled to the selected memory unit 201.
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Citations
30 Claims
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1. A memory comprising:
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a plurality of self-contained memory units for storing data; a plurality of shift registers, each said shift register including a first parallel data port coupled to a data port of a corresponding one of said self-contained memory units and a serial port; interconnection circuitry coupled to a second parallel data port of each said shift register; and control circuitry operable to control the exchange of data between a selected one of said memory units and said interconnection circuitry via said parallel ports of said shift register coupled to said selected memory unit and the exchange of data with said selected one of said memory units through said serial port of said shift register coupled to said selected memory unit. - View Dependent Claims (3, 4, 5, 6, 7, 8)
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2. The memory of claim I wherein said control circuitry is operable to control the exchange of a block of data from a first one of said memory units to a second one of said memory units via said interconnection circuitry and said shift registers respectively coupled to said first and second memory units.
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9. A memory system comprising:
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a plurality of memory subsystems each comprising; an array of rows and columns of memory cells; row decoder circuitry for selecting a said row of cells in response to a row address; and sense amplifier circuitry for reading and writing data to and from a said cell of a selected said row and a selected said column; and a plurality of shift registers each for controlling the exchange of data with a respective said subsystem, wherein each said shift register including a serial port for inputting and outputting data for exchange with said respective said subsystem. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A memory device comprising:
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a plurality of self-contained memory units for storing data, each including an array of dynamic random access memory cells arranged in rows and columns, circuitry for addressing selected ones of said cells, and sensing circuitry for reading and writing data into said selected cells; a plurality of shift registers, each said shift register including a first parallel data port coupled to a data port of a corresponding one of said self-contained memory units and a serial port coupled to device input/output circuitry; interconnection circuitry coupled to a second parallel data port of each said shift registers; and control circuitry operable to control the exchange of data between selected said cells of a selected one of said memory units and said interconnection circuitry via said parallel ports of corresponding said shift registers and to control the exchange of data between selected said cells and said device input/output circuitry via said serial port of said corresponding shift register. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. A method for performing a data transfer in a memory including a plurality of self-contained memory units, each having an array of memory cells arranged in rows and columns and associated addressing circuitry and a plurality of shift registers each coupling a respective memory unit with interconnection circuitry, the method comprising the steps of:
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reading a plurality of bits from a selected row of cells in a first one of the memory units; passing the plurality of bits through the shift register coupled to the first memory unit to the interconnection circuitry; passing the plurality of bits through the shift register coupled to a second one of the memory units; and writing the plurality of bits into a row in the second memory unit. - View Dependent Claims (27)
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28. A processing system comprising:
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a graphics processor for processing graphics data; a video processor for processing video data; a unified frame buffer comprising; a plurality of self-contained memory units; a plurality of shift registers, each said shift register including a first parallel data port coupled to a data port of a corresponding one of said self-contained memory units; interconnection circuitry coupled to a second parallel data port of each said shift register; and control circuitry operable to control the exchange of data between a selected one of said memory units and said interconnection circuitry via said shift register coupled to said selected memory unit; and wherein said graphics processor is coupled to a selected one of said plurality of self-contained memory units for exchanging data therewith; and said video processor is coupled to another one of said plurality of self-contained memory units for exchanging data therewith. - View Dependent Claims (29, 30)
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Specification