Disabling sense amplifier

• US 5,473,567 A
• Filed: 08/31/1994
• Issued: 12/05/1995
• Est. Priority Date: 03/31/1993
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: McClure, David C.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/298,766
• Time in Patent Office: 461 Days
• Field of Search: 365/189.02, 365/207, 365/208, 365/230.02, 365/230.03, 365/205, 365/190, 327/51, 327/52, 327/53, 327/57
• US Class Current: 365/208
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type

Abstract

A memory system that includes a memory array having at least two pairs of data lines, first and second data lines that correspond to columns in the memory array. The memory array also includes two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to the first data lines and a second disabling sense amplifier circuit connected to the second data lines, wherein the disabling sense amplifier circuits produce output signals and may be enabled and disabled. A selection signal is provided for selectively enabling and disabling the disabling sense amplifier circuits, wherein one pair of data lines may be selected. An amplification circuit connected to the disabling sense amplifier circuits provides for amplifying the output signals from the disabling sense amplifier circuits.

Claims

1. A multiplexing sense amplifier circuit for use with a memory array comprising:

a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and

a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage.

4. The multiplexing sense amplifier circuit of claim 1 further comprising:

an amplifier stage connected to the true output and the complement output of the second stage, the amplifier having a pair of outputs, wherein the amplifier generates logic 1 and logic 0 signals at the pair of outputs in the amplifier stage in response to signals from the true output and complement output of the second stage.

2. A multiplexing sense amplifier circuit for use with a memory array comprising:

a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and

a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage, wherein both outputs of the disabling sense amplifier circuits are forced low in response to disablement of one of the two disabling sense amplifier circuits.

5. The multiplexing sense amplifier circuit of claim 2, wherein said second stage comprises a first pair of transistors and a second pair of transistors, each pair of transistors having a first transistor connected in parallel with a second transistor in the pair, the gate of the first transistor in the first pair being connected to the true output of the first disabling sense amplifier circuit, the gate of the second transistor in the first pair being connected to the true output of the second disabling sense amplifier circuit, the gate of the first transistor in the second pair being connected to the complement output of the first disabling sense amplifier circuit, and the gate of the second transistor in the second pair being connected to the complement output of the second disabling sense amplifier circuit, wherein the two pairs of transistors control the true output and the complement output of the second stage.

6. The multiplexing sense amplifier circuit of claim 5, wherein the amplifier stage is a p-channel cross-coupled amplifier comprising two p-channel FETs, each p-channel metal-oxide transistor having a gate connected to a drain of the other p-channel FET, and two n-channel FETs, each n-channel FET having a drain connected to the drain of a p-channel FET, wherein the true output of the second stage is connected to the gate of the first n-channel FET and the complement output of the second stage is connected to the gate of the second n-channel FET.

7. The multiplexing sense amplifier circuit of claim 5, wherein the second stage comprises a pair of current mirrors, a first current mirror and a second current mirror, the first current mirror having an output controlled by the outputs of the first and second disabling sense amplifier circuits and the second current mirror having an output controlled by the outputs of the first and second disabling sense amplifier circuits.

3. A multiplexing sense amplifier circuit for use with a memory array comprising:

a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and

a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage, wherein the second stage is a multiplexing sense amplifier.

8. A multiplexing sense amplifier circuit for use with a memory array comprising:

a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and

a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage, wherein each current mirror includes four control transistors for controlling the output of the current mirror.

9. The multiplexing sense amplifier circuit of claim 8, wherein the first control transistor has its gate connected to the true output of the first disabling sense amplifier circuit, the second control transistor is connected in parallel with the first control transistor and has its gate connected to the true output of the second disabling sense amplifier circuit, the third control transistor has a gate connected to the complement output of the first disabling sense amplifier circuit, and the fourth control transistor is connected in parallel with the third control transistor and has a gate connected to the complement output of the second disabling sense amplifier circuit.

10. A multiplexing sense amplifier circuit for use with a memory array comprising:

a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and

a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage, wherein each disabling sense amplifier circuit includes two current mirrors.

11. A multiplexing sense amplifier circuit for use with a memory array comprising:

a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and

a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage, wherein each disabling sense amplifier circuit includes a p-channel cross-coupled amplifier.

12. A multiplexing sense amplifier circuit for use with a memory array comprising:

a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and

a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage, wherein each disabling sense amplifier includes a differential amplifier.