Disabling sense amplifier
First Claim
1. A multiplexing sense amplifier circuit for use with a memory array comprising:
- a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and
a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage.
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Accused Products
Abstract
A memory system that includes a memory array having at least two pairs of data lines, first and second data lines that correspond to columns in the memory array. The memory array also includes two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to the first data lines and a second disabling sense amplifier circuit connected to the second data lines, wherein the disabling sense amplifier circuits produce output signals and may be enabled and disabled. A selection signal is provided for selectively enabling and disabling the disabling sense amplifier circuits, wherein one pair of data lines may be selected. An amplification circuit connected to the disabling sense amplifier circuits provides for amplifying the output signals from the disabling sense amplifier circuits.
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Citations
12 Claims
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1. A multiplexing sense amplifier circuit for use with a memory array comprising:
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a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage. - View Dependent Claims (4)
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2. A multiplexing sense amplifier circuit for use with a memory array comprising:
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a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage, wherein both outputs of the disabling sense amplifier circuits are forced low in response to disablement of one of the two disabling sense amplifier circuits. - View Dependent Claims (5, 6, 7)
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3. A multiplexing sense amplifier circuit for use with a memory array comprising:
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a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage, wherein the second stage is a multiplexing sense amplifier.
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8. A multiplexing sense amplifier circuit for use with a memory array comprising:
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a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage, wherein each current mirror includes four control transistors for controlling the output of the current mirror. - View Dependent Claims (9)
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10. A multiplexing sense amplifier circuit for use with a memory array comprising:
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a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage, wherein each disabling sense amplifier circuit includes two current mirrors.
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11. A multiplexing sense amplifier circuit for use with a memory array comprising:
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a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage, wherein each disabling sense amplifier circuit includes a p-channel cross-coupled amplifier.
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12. A multiplexing sense amplifier circuit for use with a memory array comprising:
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a disabling sense amplifier stage having at least two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to a first input line and a first complement input line and a second disabling sense amplifier circuit connected to a second input line and a second complement input line, each disabling sense amplifier circuit having two outputs, a true output and a complement output, and a select input, responsive to a select signal, for enabling or disabling the disabling sense amplifier circuits, wherein the first disabling sense amplifier circuit is disabled when the second disabling sense amplifier circuit is enabled and when the first disabling sense amplifier circuit is enabled, the second disabling sense amplifier circuit is disabled and wherein selection of signals from one of the two disabling sense amplifier circuits may be accomplished; and a second stage having a true output and a complement output and multiple true and complement inputs, the second stage true and complement inputs being connected to the true and complement outputs of the disabling sense amplifier stage, wherein data on the true output and the complement output of the second stage are controlled by data on the outputs of the disabling sense amplifier stage, wherein each disabling sense amplifier includes a differential amplifier.
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Specification